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IEEE 1588 Slave and Master Clock - Chip on FPGA
IPC1710
Features

IEEE 802.11 b PHY
Features

IEEE 802.11ad (WiGig 60GHz) LDPC Decoder
Features

IEEE 802.11n/802.11ac (WiFi) LDPC Decoder
Features

IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
Features

IEEE 802.16d WiMAX PHY
Features

IEEE 802.16e PHY
Features

IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
MACSEC-10G
Features

IEEE 802.3bw Automotive Ethernet PHY - OmniPHY
OMNI_AUTOPHY_TSMC40LP
Features

IEEE Floating Point Unit
A2F
Features

IEEE-1394 SIP
Features

IEEE-754 Floating Point FFT/IFFT IP core
Features

IEEE802.3an 10GBASE-T LDPC decoder
Features

IEEE802.3an 10GBASE-T LDPC encoder
Features

iLIN
Features

IMA ADPCM Sound Compressor
Features

IMA ADPCM-SO1
Features

IMS16E
Features

In-System Sources & Probes

IndigoVision's Control Center
Features

iniADPLL
Features

iniCAN
Features

iniCAN - CAN 2.0B compliant Controller
Features

iniCPU
Features

iniCPU, a 8-bit microprocessor
Features

iniDSP, a 16-bit fixed-point general purpose DSP
Features

iniFUART
Features

iniG704-E1
Features

iniHDLC
Features

iniLCDC
Features

iniSCI_master
Features

iniSCI_slave
Features

iniUART
Features

Inrevium V-by-One HS IP Core
TIP-VBY1HS
Features

Instruction-Side On-Chip Memory (ISOCM) Bus
Features

INT 1020 Giga-bit Multi-port Switch
Features

INT-1000 10/100/1000 M bit MAC EngineC
Features

INT-10000 10-Gbit Ethernet MAC Engine
Features

Int-11400 3DES Triple DES Crypto-processor Core
Features

Int-11500
Features

Int-11600 AES Advanced Encryption/Decryption Standard Core
Features

INTCmodule
Features

Integrated Core Solution (ICS)
Features

Integrated Solution - AMBA AXI Bridge for PCI Express Gen1/Gen2 x1/x4 Controllers/SBSUBAXIPCIEX
Features

Integrated Solution - PCI Express to AHCI-compliant SATA Host Controller/SBSUBPCIE2SAT
Features

Integrated Solution - PCI Express to DDR Controller/SBSUBPCIE2DDR
Features

Integra™ AXI Memory Controller for Embedded SRAM/ROM
Features

Integra™ Control Network
Features

Integra™ AHB Memory Controller for Embedded SRAM/ROM
Features

Integra™ ML Network (Multi-Layer Network)
Features

Integra™ QoS Engine
Features

INTELLITM DDR2/DDR3 800Mbps to 1600Mbps SDRAM MEMORY CONTROLLER
Features

INTELLI™ DDR1/2 800Mbps PHY+DLL FOR HIGH-PERFORMANCE SDRAM MEMORY CONTROLLERS
Features

INTELLI™ DDR1/DDR2 800Mbps MEMORY CONTROLLER
Features

INTELLI™ DDR2/DDR3 1600Mbps PHY+DLL AND I/O FOR HIGH-PERFORMANCE DRAM MEMORY CONTROLLER
Features

INTELLI™ DDR2/DDR3 1600Mbps PHY+DLL FOR HIGH-PERFORMANCE DRAM MEMORY CONTROLLERS
Features

INTELLI™ DDR3 1.6Gbps PHY+DLL AND I/O FOR HIGH-PERFORMANCE DRAM MEMORY CONTROLLERS
Features

INTELLI™ DDR3 1600Mbps PHY+DLL HARD MACRO FOR HIGH-PERFORMANCE SDRAM MEMORY CONTROLLERS
Features

INTELLI™ GDDR MEMORY CONTROLLER FOR GRAPHICS
Features

INTELLI™ LOW POWER DDR MEMORY CONTROLLER
Features

Intelli™ Memory Interface

Inter INTEGRATED CIRCUIT (I2C)
Features

INTERFACE IPS

Interlaken Controller IP Core
Features

Interlaken IP
Features

Interlaken Protocol
Features

Interlaken VIP
Features

Interlaken, 100G for 28nm devices

Interlaken, 100G, 12 Lanes

Interlaken, 100G, 20 Lanes

Interlaken, 150G, 24 Lanes

Interlaken, 40G, 8 Lanes

Interlaken, 50G for 28nm devices

Interlaken-PHY (ILKN-PHY)
Features

Interleaver / De-interleaver
Features

Interleaver/De-Interleaver
Features

Inventra CON-DEC, Concatenated Decoder; ~5,700 gates documented (user parameterised design), size and max clock depends on technology and symbol rate and channe

Inventra CON-ENC, Concatenated Encoder; 15,000 - 48,000 gates (user parameterised design), size and max clock depends on technology, symbol rate and channel par

Inventra DCT-8X8, 8X8 Discrete Cosine Transform; 20,000-34,000 gates (user parameterised design), up to 160 MHz

Inventra DMAXN, Multi-Channel DMA Controller; 2,000+ gates (configurable), max clock depends on technology and number of channels.

Inventra DSP-DDS, Direct Digital Synthesizer Core; 1,500 gates, 50MHz

Inventra E1-DFRM, E1 Deframer; 1,300 gates, 90Mhz

Inventra E1-KIT-R, E1 Framing/Deframing Kit (Re-Ordering Add/Drop); 13,800 gates, 90MHz

Inventra E1-KIT-S, E1 Framing/Deframing Kit (Selective Add/Drop); 8,200 gates, 90MHz

Inventra FBUS-LIB-F, FISPbus Foundation Library; 100+ gates (configurable), 100Mhz+

Inventra FEMI, FISPbus External Memory Interface; 8,500 gates (configurable), 75Mhz

Inventra FFT, Fast Fourier Transform, Inverse FFT/Fast Convolver; 20,000 gates typical (user parameterised design), size and max clock depends on technology and

Inventra FIR, Linear Phase FIR Filter; 5,000-65,000 gates typical (user parameterised design), size and max clock depends on technology and filter order.

Inventra G711-CMP, G.711 PCM Compressing Function; 500 gates

Inventra G711-EXP, G.711 PCM Expanding Function; 500 gates

Inventra G726-COMx1, Single Channel G.726 ADPCM Compact Core; 7,000 gates, 30MHz

Inventra G726-COMxN, Multi-Channel G.726 ADPCM Compact Core; 8,000 gates, 50MHz

Inventra G726-LPx1, Single Channel G.726 ADPCM Low Power Core; 16,000 gates, 1MHz

Inventra G726-LPxN, Multi-Channel G726 ADPCM Low Power Core; 20,000 gates, <17MHz

Inventra GCI-IFACE, GCI Interface; 5,000-6,000 gates, 40MHz

Inventra HDLC-CORE, Single Channel HDLC Core; 1,850 gates, 20Mhz

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