DesignCon® is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection, and design verification.
WHAT: Synopsys will be showcasing its latest developments in the DesignWare SuperSpeed USB 3.0 and DDR IP in Synopsys Booth #216. The DesignWare IP for PCI Express 3.0 will be shown in the LeCroy Booth #109. In addition, Synopsys will be participating in a number of presentations, tutorials and panels at the show.
WHEN: February 2-3, 2010
WHERE: Santa Clara Convention, 5001 Great America Pkwy., Santa Clara, CA 95054
EXHIBIT HOURS:
Tuesday, February 2 | 12:30pm - 6:30pm | |
Wednesday, February 3 | 12:30pm - 6:30pm | |
Synopsys Highlights at DesignCon:
DesignWare IP Booth #216
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This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second. | |
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Witness full-speed write and read data eyes up to 1600 Mbps, automatic process, voltage and temperature (PVT) drift compensation, internal data eye width measurements, clock jitter measurements and the capabilities within the DDR IP. | |
LeCroy Booth #109
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The demo will utilize the LeCroy's SimPASS PE protocol application to display and analyze the PCI Express 3.0 traffic generated by the DesignWare PCI Express Verification IP when verifying a design. See how SimPASS enables you to eliminate potential flaws in the data and transaction packets from the I/O stream, allowing developers to more thoroughly test and debug the logic design prior to going into silicon. | |
Presentations, Panels and Tutorials:
- Presentation: Interconnect Considerations for DDR Timing Closure beyond 1600 Mbps
- Business Forum Panel: The Last Mile: Outsourcing Production
- Tutorial: Best Practices for IP Re–Use
- Tutorial: Top System-On-a-Chip Power Management Verification Issues and Their Solutions
- Tutorial: Functional Verification Planning and Management for Designers: Navigating From Specification to Functional Closure
- Panel: Extent of Dynamic Validation in Power Managed Designs
6-WA4 Interconnect Considerations for DDR Timing Closure beyond 1600 Mbps
Wednesday, February 3 | 11:05 am - 11:45 am
Speaker: John Ellis, Senior Staff R&D Engineer, Synopsys, Inc.
JEDEC's DDR3 standard supporting 2133 Mbps will make closing timing extremely challenging. Implementers will have to scrutinize timing budgets in order to close timing. Deskew silicon technology will no longer be optional. For successful timing closure, signaling effects once considered secondary will now claim a significant portion of the timing budget. By definition, DDR3 introduces skew into timing budgets by capturing single ended data signals with differential strobes. Signaling effects such as modal dispersion and crosstalk timing impacts now must be addressed with care. Use of microstrip on printed circuit boards must be considered more cautiously as this can be a significant source of signal skew if not managed carefully.
BF-T3 | Business Forum Panel - The Last Mile: Outsourcing Production
Tuesday, February 2 | 2:00 pm - 3:30 pm
Chairperson: Ron Wilson, Executive Editor, EDN Worldwide
Speakers: John Koeter, Vice President of Marketing, Solution Group, Synopsys; Kalar Rajendiran Sr. Director, Marketing, eSilicon; Todd Oseth, President and CEO, Neterion, Inc.; Bob Quinn, Founder, Chairman and CTO, 3Leaf Systems; Brad Paulsen Vice President, Business Management, TSMC
Continuous cost-down pressure characterizes the semiconductor market and is the driver behind the industry's dis-aggregated infrastructure. In the 70's, we outsourced packaging and test; in the early 80's, EDA; in the late 80's, wafers; and in the early to mid 90's, we outsourced IP and front-end design services.
Is there another opportunity to outsource? Operations is the next semiconductor value chain link that will be outsourced by leading edge industry thinkers to maximize "return-on-design," reduce overhead costs, and drive profits to the bottom line.
Who will benefit? Whether a small semiconductor company or the IC division of a large systems company seeking to alleviate the need for temporary technical help; or larger companies looking to permanently slash overhead and reinvest resources in core competencies, operations outsourcing is the next dis-aggregation trend that will further business success.
TF-MP6 | Tutorial - Best Practices for IP Re–Use
Monday, February 1 | 9:00 am - 12:00 pm
Chairperson: Warren Savage, President and CEO, IPextreme, and GSA IP Working Group Chair
The licensing and use of Semiconductor Intellectual Property is a key element of the semiconductor industry today. Yet, customers and suppliers alike still complain that the business model is broken and quality remains a significant impediment to the health of the industry.
Leaders from the Global Semiconductor Alliance (GSA) IP Working Group will offer a tutorial regarding the common challenges facing IP reuse today and best practices and resources that are available to companies today from the GSA. Among the topics:
- Metrics and tools available for quantifying the quality of IP
- Making a Return–on–Investment calculation for buying or making IP
- Best practices and norms on legal contracts
- Best practices for documenting IP
