TF-MA10 | Tutorial - Top System-On-a-Chip Power Management Verification Issues and Their Solutions

Monday, February 1 | 9:00 am - 12:00 pm

Speakers: Bhanu Kapoor, Consultant/Owner, Mimasic; Dr. Shireesh Verma, Verification Manager, Conexant; Shankar Hemmady, Principal Engineer, Synopsys; Dr. Kaushik Roy, Professor, Purdue University; Amit Kumar, Senior Program Manager, SiRF Technologies

Power consumption has become one of the most important differentiating factors for semiconductor products. Voltage is the strongest handle for managing chip power consumption. We look in detail at some of key power management techniques such as Power Gating, Adaptive Voltage Scaling and Active Body-Bias that leverage voltage as a handle.

We discuss the implications of power management architecture design, partitioning and new challenges in functional validation. We look at top power management verification issues such as reset out of wake-up, power connectivity, always-on buffers, switching management, state retention and sequencing protocol, and decap placement issues in detail.

TF-MP1 | Tutorial-Functional Verification Planning and Management for Designers: Navigating From Specification to Functional Closure

Monday, February 1 | 1:30 pm - 4:30 pm

Speakers: Andrew Piziali, Independent Consultant, Association of Design Verification Engineers; Avi Ziv, Research Staff Member, IBM; Shankar Hemmady, Principal Engineer, Synopsys

This tutorial teaches state-of-the-art techniques and methodologies that are used in the industry today for planning, monitoring and assessing verification progress. Planning, monitoring and assessment of the verification process are essential for predictable, successful verification. Quantifying the scope of the verification problem, specifying its solution and measuring verification progress against this plan dramatically reduces schedule uncertainty and provides an adaptive framework for accommodating design and schedule changes. This planning process provides the information necessary to predict the state of the verification process for risk analysis and management. Overall, good planning, monitoring and assessment prevent late schedule and quality surprises.

TP-T3 | Technical Panel - Extent of Dynamic Validation in Power Managed Designs

Tuesday, February 2 | 3:45 pm – 5:00 pm

Chairperson: Bhanu Kapoor, President and Founder, Mimasic

Speakers: Ed Sperling, Editor in Chief, System-Level Design and Editorial Director, Low-Power Engineering; Dr. John Goodenough, Director, Design Technology, ARM; Prapanna Tiwari, Corporate Applications Engineer, Synopsys; Amit Kumar, Senior Program Manager, SiRF Technologies;

This panel looks into the new challenges in validation of designs using above mentioned power management techniques. Some of the initial techniques focused on structural checking of power management issues combined with limited amount of simulation using methods like x–injection. More recent advances are resulting in enhancement of simulators to induce effects of power gating, state retention, power sequencing, and voltage changes.

There exists data from power managed designs that points to structural checkers as the central tool for validation of large class of issues power management issues even including issues such as incorrect reset on wake–up.

To what extent do we need dynamic simulation to validate power management issues? Does power management validation significantly increase the amount of simulation needed to validate the design or is it only incremental when combined with smart structural checkers? Also, what is the right level of abstraction at which dynamic simulation should be carried out?

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven interface and analog IP solutions for system-on-chip designs. Synopsys' broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, HDMI, MIPI and Ethernet. The analog IP family includes Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transaction-level models to build virtual platforms for rapid, pre-silicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http:// www.synopsys.com/designware.

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About Synopsys

Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

SOURCE Synopsys, Inc.