Who:
Real Intent, the leader in formal verification from spec to sign-off, invites the Design Automation Conference (DAC) attendees to its booth to learn more about its automatic formal, clock and timing verification software and the "Assertion Density Paradox."
What: Assertion Density Paradox
With most Assertion-Based Verification (ABV) solutions, if one assertion is hard to prove, then many assertions are even harder. However, with Real Intent's patented technology, the opposite can be true -- having many assertions can be easier to prove than just one.
When/Where:
Monday - Wednesday, July 24-26, 9:00 AM to 6:00 PM Thursday July 27, 9:00 AM to 1:00 PM Booth #706 Moscone Convention Center, San Francisco, CAReal Intent's EnVision Family
Designed with the most challenging ABV needs in mind, Conquest moves beyond block-level verification to cluster-level verification. The combination of the industry's most powerful formal Convergence Engine™ with an assertion visualization capability allows for more capacity and interactivity, and higher productivity than alternative solutions. With Conquest, users can verify their design using Property Specification Language (PSL) assertions, SystemVerilog Assertions (SVA), or Open Verification Library (OVL) checkers.
Ascent offers automatic checks derived from the Register Transfer Level (RTL) design to verify logic and find bugs even before simulation. It supports PSL and SVA constraints and includes the Ascent SimPortal, which links to dynamic simulation. Ascent with the Convergence Engine delivers higher performance and faster proofs. It is often used as a signoff step before the RTL code is checked into the design process. It finds sequential design errors, including array bounds violations, full and parallel case pragma violations, Finite State Machine (FSM) deadlocks and dead code. These errors are detected automatically without testbenches or running simulations.
Clock Intent Verification verifies the functionality of the user's cross domain clocking scheme and quickly identifies errors with its new debugging features.
PureTime, a timing-exception verifier, detects timing exception errors that create schedule delays, chip respins or failing hardware. It proves the correctness of timing exceptions created by designers, or those delivered with Intellectual Property (IP), using exhaustive formal analysis. PureTime works throughout the entire design flow, with RTL or design netlists.
Information and Registration:
To set an appointment with Real Intent at DAC, please contact Rich Faris, 408-839-6510.
For more information about Real Intent, please visit www.realintent.com.
Please visit www.dac.com for more information about DAC.
About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including Sun Microsystems, ATI, Marvell Technology Group, nVidia, and NEC Electronics, use Real Intent software.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: Email Contact.
EnVision, Conquest, Ascent, Convergence Engine, SimPortal, PureTime, Clock Intent Verification are trademarks of Real Intent, Inc. All other trademarks or registered trademarks are property of their respective owners.
Press contacts: Rich Faris Real Intent Vice President Marketing and Business Development (408) 830-0700 x212 Email Contact Georgia Marszalek Valley PR for Real Intent (650) 345-7477 Email Contact
