August 20th, Santa Clara, California

SANTA CLARA, Calif.--(BUSINESS WIRE)--July 30, 2002--

Who:

Verification leaders -- Co-Design Automation, Novas, and Real Intent -- invite design and verification engineers and managers, who are designing complex, multi-million gate chips and systems to attend their seminar with product demonstrations, and learn more about how assertion-based verification and behavior-based debug can reduce the verification bottleneck.

What:

At the verification seminar, attendees will learn how to reduce verification time and see demonstrations of proven debug and verification solutions.

Noted designer, design team leader and author, James M. Lee, will speak about his vision for assertion-based verification.

    When:
    Tuesday, August 20, 2002
    9am-noon

Where:

Santa Clara Hilton, 4949 Great America Parkway, Santa Clara, California

Registration Information:

To register, please visit http://www.realintent.com/seminar/seminar_registration_form.html.

Agenda:

8:30 - 9:00      Continental breakfast
9:00 - 9:05      Welcome
9:05 - 9:30      Keynote - James M. Lee
9:30 - 9:45      Break
9:45 - 10:00     SUPERLOG(R) and Assertion-Based Simulation, Co-Design
10:00 - 10:15    Verix(tm) and Assertion-Based Formal Verification,
                  Real Intent
10:15 - 10:30    Verdi(tm) Behavior-Based Debug System, Novas
10:30 - 11:00    Q&A Session
11:00 - 12:00    In-Depth Product Demos

About the Co-hosts:

Co-Design Automation, Inc., is an EDA company focused on design verification solutions for large-scale electronic designs. It is privately held and funded by Intel Capital Corporation and Redwood Venture Partners Inc., along with investors from the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL and the first fellow at Cadence Design Systems Inc. (NASDAQ: CDN - News), and Peter Flake, creator of the HILO HDL. In 1999, Co-Design announced the SUPERLOG language, now utilized by multiple partner companies. Its products -- Systemsim and Systemex -- are achieving success throughout the electronics industry worldwide in design and verification applications. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.

Novas is the pioneer of knowledge-based debug systems that reduce the functional verification costs for complex IC designs. Building upon the strength of its market-leading Debussy® Knowledge-Based Debug System, Novas' second-generation Verdi(TM) Behavior-Based Debug System improves the efficiency of designers in the system-on-chip era with advanced design exploration and debug capabilities. These allow design teams to better understand and analyze complex or unfamiliar design behavior, and cuts by half or more the time it takes to locate, isolate and understand the root causes of design problems. There are more than 7,000 Novas systems in use today at customer sites worldwide. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information visit www.novas.com or send email to info@novas.com.

Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven Verix formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC). For more information, email: info@realintent.com, web: http://www.realintent.com.

Note to Editors: All trademarks and tradenames are the property of their respective owners.

     PR for Co-Design
     Nanette Collins, 617/437-1822
     nanette@nvc.com
            or
     PR for Novas
     Laurie Stanley, 510/656-0999
     laurie@wiredislandpr.com
            or
     ValleyPR for Real Intent
     Georgia Marszalek, 650/345-7477
     Georgia@ValleyPR.com