LOS ALTOS, Calif. & SANTA CLARA, Calif.--(BUSINESS WIRE)--May 28,
2002--
Utilizing Assertions To Improve Embedded Systems, IP Verification Productivity To Be Revealed To Designers, Verification Engineers
A hands-on tutorial to train hardware designers on assertion-based validation for intellectual Property (IP)-based embedded system verification will be held during the 39th Design Automation Conference (DAC) at the Ernest N. Morial Convention Center in New Orleans. The tutorial will be held Tuesday, June 11, from 2-5 p.m. in Room 293.
It is presented by Co-Design Automation, Inc., a provider of electronic system simulation, and Real Intent, Inc., a leading supplier of assertion-driven formal verification software.
Set up for designers to get hands-on experience, the tutorial will use available software, demonstrating a formal functional verification and system simulation environment for implementing and using IP within an embedded system. Designers will utilize assertions across an embedded system, learning how to quickly verify IP blocks with formal verification tools, and reuse the same test structures within an IP-based platform, driven by hardware and software tests. Benefits of combining formal verification and system simulation, as well as the application of software-driven platform verification, will be demonstrated.
Focus will be placed on Co-Design and Real Intent Superlog® Assertions (CRSA), recently donated to Accellera for inclusion in the SystemVerilog standard. A standard ARM-based platform will be used with the ARM core operating an AMBA bus interfacing with the IP.
Registration may be done online at: http://www.dac.com
About Real Intent
Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven Verix formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC).
Real Intent is located at 3910 Freedom Circle, Suite 102A, Santa Clara, CA 95054, tel.: (408) 982-5444, fax: (408) 982-5443, email: info@realintent.com, web: http://www.realintent.com.
About Co-Design Automation
Co-Design Automation, Inc., is an EDA company focused on design verification solutions for large-scale electronic designs. It is privately held and funded by Intel Capital Corporation and Redwood Venture Partners Inc., along with investors from the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL and the first fellow at Cadence Design Systems Inc. (NASDAQ: CDN - News), and Peter Flake, creator of the HILO HDL. In 1999, Co-Design announced the SUPERLOG language, now utilized by multiple partner companies. Its products -- Systemsim and Systemex -- are achieving success throughout the electronics industry worldwide in design and verification applications. Corporate headquarters is in Los Altos, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.
Verix and Real Intent are trademarks of Real Intent. SUPERLOG is a
registered trademark and SYSTEMSIM, SYSTEMEX, CBlend are trademarks of
Co-Design Automation, Inc. Verilog is a trademark of Cadence Design
Systems, Inc. Real Intent and Co-Design Automation acknowledge
trademarks or registered trademarks of other organizations for their
respective products and services.
Contact:
Public Relations for Co-Design
Nanette Collins, (617) 437-1822
nanette@nvc.com
or
Co-Design
David Kelf, (617) 571-9883
davek@co-design.com
or
Public Relations for Real Intent
Georgia Marszalek, (650) 345-7477
Georgia@ValleyPR.com
or
Real Intent
Steve Pollock, (408) 982-5412
pollock@realintent.com
