Extreme DA Declares Victory in Timing Analysis Performance / Capacity Race: Moves to Raise the Bar for Statistical Analysis

SANTA CLARA, Calif. — (BUSINESS WIRE) — July 21, 2009 Extreme DA™, the leader in new-generation timing analysis (TA) software, announced it has reached TA performance and capacity levels unmatched in the industry. Leveraging their extensive software expertise in multi-threading and memory utilization, Extreme DA will focus on bringing the runtime and memory footprint for statistical TA to the same levels as today’s corner based analysis.

 

With GoldTime, Extreme DA has been able to minimize TA performance as a sign-off bottleneck. Based on proven ThreadWave technology and advanced multi-threading, overnight TA runs for 100 million instance designs have become routine. “We have reached a performance level that has allowed our customers to focus their efforts on other parts of the flow which have become the new bottlenecks of sign-off analysis,” said Ruben Molina, Director of Technical Marketing. “At Extreme DA, we think that further development in speeding up corner-based TA has reached the point of diminishing returns for most customers. While our competitors are working furiously to catch up, we’ve already reached TA performance levels that will satisfy the largest customers designs manufactured in the latest process technologies.”

Statistical Timing Analysis to Replace Corner Based Approach

Corner based sign-off of designs targeted to silicon processes at 40nm and below, requires large derating factors to account for on die process variation. When coupled with a foundry’s corner based libraries, the resulting conservatism dramatically limits the ability to reach timing closure. Furthermore, modeling interconnect variation requires the addition of a number of corners to the sign-off process. Because statistical TA does not have this pessimism, it will become the only realistic and viable approach to sign-off without overdesign of ICs.

“The trend to greater complexity will push the average design size to more than 20 million instances by year’s end with some ICs reaching over 200 million instances in 2010,” said Mustafa Celik, CEO. “Statistical TA must be done to control variation but does require more calculations and computations be done. We are taking a proactive approach to bring runtime and capacity to the same levels that we have achieved with corner based TA. Extreme DA GoldTime addresses designers’ TA needs today and is well positioned to address their statistical TA needs in the future.”

About GoldTime — The New Standard in Sign-off Timing

GoldTime is the new-generation timing analysis technology that delivers 5X better combination of speed and capacity. With its new from-the-ground-up architecture, designers can sign-off with certainty and achieve faster timing closure. Whether verifying a current generation design across corners or doing a statistical analysis to optimize the performance, power and yield for 40nm ICs, GoldTime delivers the answers while the competition is still figuring out the results.

About Extreme DA

Headquartered in Santa Clara, Calif., venture-funded Extreme DA develops and licenses software products for the timing sign-off of 65- and 45-nanometer integrated circuits. The company’s investors include Foundation Capital, IT-Farm Corporation, and Lanza techVentures. For the latest news and information on Extreme DA, visit www.extreme-da.com or write to Email Contact.

Extreme DA and GoldTime are trademarks of Extreme DA. All other legal marks are the property of their respective owners.

 



Contact:

Armstrong and Associates, Inc.
PR Counsel for Extreme DA
Jean Armstrong, 503-477-5434
or
Extreme DA
Ruben Molina, 408-588-1112
Director of Technical Marketing

 

Featured Video
Latest Blog Posts
Vijay ChobisaSiemens EDA
by Vijay Chobisa
The Rise of Custom Acceleration
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Nomination Deadline for Phil Kaufman Award and Hall of Fame: June 30
Jobs
Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Hardware Engineer for PTEC Solutions at Fremont, California
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Upcoming Events
2024 IEEE Symposium on VLSI Technology & Circuits at HILTON HAWAIIAN VILLAGE HONOLULU HI - Jun 16 - 20, 2024
Design Automation Conference (DAC) 2024 at Moscone West, San Francisco CA - Jun 23 - 27, 2024
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise