Concept Engineering released SpiceVision, a new interactive visualization tool that helps chip designers debug and analyze SPICE circuits and models and fits into any EDA environment where SPICE design files are used to verify circuit behavior. SpiceVision produces clean, easy-to-read transistor-level schematics from complex SPICE descriptions, reducing the design and debug time for engineers who work at the SPICE netlist level. SpiceVision is a unique tool that can take SPICE descriptions and provide intuitive design navigation, schematic views, and design documentation, the company said.
Icinergy Software released version 3 of SOCarchitect, an integrated physical design, analysis and optimization environment that allows designers to quickly capture the earliest possible physical representation of a complex ASIC or SOC, and use the model to drive downstream flows. This global view of the design helps uncover fundamental design flaws when they are easiest to fix - well before RTL coding begins, Icinergy claims.
SOCarchitect release 3 introduces significant new timing analysis capabilities that improve visibility and predictability throughout the synthesis and place-and-route flow. Built-in timing analysis creates an accurate picture of chip-level timing to guide the synthesis process. A compact, high-capacity database allows users to maintain a consistent model of the design right from concept through to GDSII. The new release also includes a number of user-customizable "wizards" that simplify repetitive design tasks, plus support for rectilinear regions.
SOCarchitect's new hierarchical timing budgeting algorithm extracts path information from the tool's virtual router to accurately predict delay through global routes. Designers can hence predict whether the design will meet timing closure, and can tune the architecture to reduce downstream iteration, the company said.
Nassda Corp. launched LEXSIM, a full-chip circuit-level simulator designed for post-layout verification of large ICs. LEXSIM is the first EDA tool able to simulate the nanometer effects of both the power network and signal interconnects for complex ICs with millions of transistors, Nassda asserted. By enabling semiconductor designers to identify and correct nanometer design problems during verification, LEXSIM can help create chips that work successfully at first silicon. Early silicon success provides a significant competitive advantage to semiconductor companies by reducing time to market and permitting a faster ramp to volume production.
Agilent Technologies Inc. introduced an RF extension to the BSIM4 Modeling Package for deep sub-micron CMOS devices used in wireless and wireline communication products, resulting in a complete DC-to-RF modeling solution. The RF extraction module, now included within the open Integrated Circuit Characterization and Analysis Program (IC-CAP) modeling software, enables highly accurate simulation of RF CMOS devices and reduces overall design time, Agilent said. The module is an update to the Agilent 85194K BSIM4 Modeling Package, a modeling solution for CMOS devices with ultra-short channel lengths that are below 0.18 microns.
Palo Alto based Q Design Automation reported that Sun Microsystems, Inc. has completed a volume licensing agreement of Q Design's Qtrek-Migrate and Qtrek-Create IC layout optimization software. Sun said it plans to use Q Design's products for migrating and optimizing existing custom IC layout to next generation processes including standard-cells, memories, caches, datapaths and control blocks.
Europe Technologies (ET) and Verisity, Ltd. announced that ET has selected Verisity's e verification language and the Specman Elite testbench automation tool for intellectual property (IP) reuse. ET is a fabless company in France that is developing SOC products for the consumer, automotive and industrial markets. ET said it selected the e language for protocol verification of IP compliance to standard protocols like USB, Ethernet and the AMBA bus. ET said it will use the e language and Specman Elite to verify and debug all new IPs developed by ET in order to improve the design quality of ET products.
Tality Corp. has appointed Mike Malone as senior VP of the company's newly formed Integrated Circuit (IC) division, which includes Tality's digital, analog and mixed signal IC design and IP offerings.
Prior to joining the company, Malone spent fourteen years with Motorola. His last post was as VP and GM within Motorola's cellular infrastructure business. During his tenure, he held numerous executive positions in sales, marketing and strategic development. Malone began his career with GTE as an engineer, later serving in project management and general management roles.
Altera Corp. released its Excalibur solutions pack, which includes development tools, debugging solutions, and operating system support for embedded systems designs. The solutions pack provides embedded software designers with access to Altera utilities and third-party applications for building system-on-a-programmable-chip (SOPC) designs with Altera's embedded processor solutions, Altera said. The Excalibur solutions pack ships as a set of CD-ROMs to all registered Excalibur developers using the Excalibur EPXA10 Development Kit. The Excalibur solutions pack includes Altera's Excalibur utilities and resources CD-ROM, which contains utilities, reference designs, OpenCore Plus evaluation IP cores, application notes, reference documents, and the Excalibur stripe simulator (ESS), as well as demo and evaluation versions of leading third-party development tools.
The Virtual Component Exchange (VCX) announced that Actel Corp. has expanded its IP offerings available on the VCX TradeFloor. By bolstering the core portfolio listed on its trading platform, VCX said it expands its IP offering to a global community that uses dedicated Actel IP cores in FPGA designs.
Also today, the VCX Exchange announced that Actel has become a member of its PLD Licensing Development Working Group. Actel has already begun actively participating in the Working Group, in order to further the group's goal of standardizing and simplifying the licensing of IP cores for FPGAs, the companies reported.
Novilit, Inc. was awarded in March a patent by the United States Patent Office. Patent number 6,356,950 was assigned to Novilit for its method for processing a data signal that accepts protocol specifications. Unlike traditional, general-purpose EDA software, Novilit has developed a software-based development environment for communications protocols. To be unveiled next month, AnyWare will accelerate the engineering design cycle for embedding protocols in ASICs, FPGAs, network processing units (NPUs), and DSPs.
InnoLogic Systems, Inc. introduced of Rev 5.0 of its ESP-CV equivalence checker. The two new main feature enhancements of the product revision include CKT, which applies formal verification at the circuit level and COV, which reports coverage holes that occur during the equivalence checking process. The two new product enhancements, which are available as upgrade options, provide better usability of ESP-CV and better and more thorough information resulting from the equivalence checking process.
InnoLogic also reported that it has received major customer endorsements from VIA Technologies, nVIDIA and Sun Microsystems. All three companies said they used InnoLogic Systems' ESP-CV equivalence checker to verify and debug specific, critical elements within their designs. With ESP-CV, the three companies said they achieved higher functional coverage and reduced the amount of time required to verify certain elements within their designs including multi-million transistor memory blocks. .ESP-CV verifies that two different design representations, such as Verilog behavioral models and transistor level views, are functionally equivalent. When differences are found, ESP-CV produces a set of binary vectors that can then be used for debug.
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