Marie R. Pistilli Women in EDA Achievement Award Winner Announced
The week ended nicely with Simplex Solutions, Inc. and Sequence Design, Inc. completing a final settlement, including product integration plans and cross-licensing agreements pursuant to the terms of the binding memorandum of understanding (March 12, 2002), pertaining to the patent infringement suit brought by Sequence against Simplex in August, 2001. As a result of the settlement and licensing agreement, the U.S. District Court in Oakland, Calif. issued a final order of dismissal.
Earlier in the week, Ann Marie Rincon, senior technical staff member at IBM Microelectronics in Burlington, Vt., is this year's winner of the Marie R. Pistilli Women in EDA Achievement Award. The announcement was made today by Jan Willis, chair of Workshop for Women in Design Automation (WWINDA) and vice president of business development at Simplex Solutions.
The award was named for the former organizer of the Design Automation Conference (DAC) Marie R. Pistilli and is presented annually to the individual who has visibly helped advance women in EDA.
"While there were many deserving and impressive candidates this year, Ann Marie Rincon's nomination stood out from the others," noted Willis. "She is a beacon of success for women seeking to build their careers on the technical track, having combined a string of technical accomplishments with strong customer relationships and industry service."
Chris King, CEO of AMI Semiconductor, nominated Rincon and concurred, "Ann Rincon has achieved pioneering accomplishments in the design community, while balancing her professional career, family, and self. Her creativity, technical strength, determination and strong work ethic have made her a change agent at IBM and in the design industry."
Rincon is recognized as a worldwide expert on ASIC design methodology, and led the development of IBM's system-on-chip (SOC) design methodology.
She was a key member of the team that defined IBM's original equipment manufacturer design methodology for high-density, high-performance ASICs. The initiative created a system for integrating IBM's chip-design technology with industry-standard software and design methods used by the EDA design community.
Rincon has filed nine patents and holds a B.S. degree in mathematics and computer science from St. Joseph's College in Rensselaer, Ind. She is an author of the Wiley Encyclopedia of Electrical and Electronics Engineering.
Rincon will receive the award during WWINDA, scheduled for Monday, June 10, from 2 p.m. - 4 p.m. at the Ernest N. Morial Convention Center in New Orleans.
Cadence Design Systems, Inc. and Credence Systems Corp. teamed to create a comprehensive technology alliance, the purpose of which being to create unique design-to-production test solutions based on an open architecture that will enable customers to manage their test-methods portfolio across the supply chain, dramatically accelerating overall time-to-market and reducing total cost-of-test, the companies said.
As the complexity of system-on-chip (SoC) and other advanced integrated circuits (ICs) have drastically increased, the total cost-of-test has risen correspondingly, Cadence and Credence explained, with as much as 75 percent of the total test costs, including test program development, simulation, characterization, debug and training, now being in non-capital equipment costs. Credence and Cadence said they plan to enable major improvements in the design-to-production test flow for tomorrow's most advanced semiconductor devices by integrating test requirements into the design process and providing open, industry-standard solutions to migrate those test parameters into the engineering validation and production test environments.
Initially, the companies will integrate industry-leading software solutions to offer a test validation environment for the IC design-for-test (DFT) engineer through the Cadence sales channel. Verification design tools (NC-Sim) from Cadence when combined with test automation and debug tools (Digital Virtual Test/Test Development Series) from Credence's subsidiary, Integrated Measurement Systems, Inc. (IMS), will create a streamlined design-to-production test flow, encompassing design implementation, test validation/debug, cyclization, and test program development. Under the agreement, both Cadence and IMS will dedicate engineering resources to provide support to the alliance.
Magma Design Automation, Inc. announced that Intersil has licensed Magma's Blast Fusion and Blast Noise software for digital IC design. Intersil said it selected Blast Fusion and Blast Noise after completing several successful benchmarks, including an ARM946E-S core. With Magma's software, Intersil said it was able to increase the speed, minimize the area and reduce the implementation time of the ARM core. Intersil said it plans to use Magma products for its next-generation 0.13-micron digital and SOC design methodology, which is mainly ARM core based.
Synopsys Inc. will cut its stake in Artisan Components to 4.32 percent from 6.48 percent, a U.S. regulatory filing showed on Tuesday. Artisan Components, said in the shelf filing with the U.S. Securities and Exchange Commission that Synopsys would be periodically selling 362,500 common shares. (A shelf filing lets a company sell securities from time to time in one or more separate offerings in amounts, at prices and on terms to be determined at the time of sale.)
Synopsys acquired the shares as part-payment when Artisan bought some of its assets in January 2001 and will receive all the proceeds from the stock sale, the SEC document said.
Virage Logic Corp. said that it plans to acquire In-Chip Systems, Inc., a privately held provider of logic platforms for SOC applications. The addition of In-Chip's technology to Virage Logic's family of SOC products will strengthen the company's leading position in the semiconductor intellectual property (SIP) market, especially for high-volume consumer applications, the companies said. In-Chip is valued at less than $20 million and is expected to close later this month.
In-Chip said its products are used by companies such as Agere, Epson, Fujitsu, Motorola, NEC, Sony, Oki, Toshiba, and Yamaha to cost-effectively improve their time-to-market and increase chip yields in the development of sophisticated high-volume SOCs for a variety of applications, including consumer products such as cell phones and two of the leading video game systems.
Verplex Systems, Inc. reported that Texas Instruments Incorporated (TI) now supports Conformal Logic Equivalence Checker (LEC) for formal verification in its ASIC flow. Four libraries have been qualified for usage with LEC in the TI ASIC flow.
Conformal LEC combines speed, performance, capacity and ease of use for the rapid and reliable formal verification of block or full-chip designs, Verplex explained. It compares register transfer level (RTL) code to flattened or hierarchical netlists for multi-million gate designs in minutes or hours, instead of days or weeks required by comparable tools.
Avant! Corp. reported that Silicon Motion Inc. has selected the Astro solution, Avant!'s physical design closure tool for large, ultra-deep-submicron (UDSM) SOC designs. As part of the SinglePass-SoC solution, Avant! said Astro provides rapid design closure of key design parameters for multi-million-gate SoC designs at 0.13-microns and below.
Axis Systems Inc. said that WIS Technologies has purchased the Xcite simulation acceleration system to verify the company's next-generation multimedia compression processors. WIS Technologies is a pioneer in the development of hardware and software solutions for the multimedia communications market, the company said. Using Axis Systems' Xcite, WIS Technologies said it verified the complex design of its new single-chip MPEG-4 streaming media encoder, which combines multiple video input formats with data compression, more than 500 times faster than software simulators.
Monterey Design Systems announced the formation of a cooperative university partnership program and that Carnegie Mellon University (CMU) has been named as a charter member.
Under the terms of the partnership, 30 licenses of the Monterey System-Driven Physical Design solution will be used in the course, which currently holds 20 students per semester. Similar courses are being prepared at other universities as part of a collaborative effort with CMU.
Prolific also announced an education program called the Prolific Research and Education Program. The program enables students to learn how to design standard cells using the same products that worldwide semiconductor companies use in their production standard cell design flows.
Charter members of the Prolific Education and Research Program include University of California, Berkeley; University of California, Santa Cruz; University of Tennessee, Knoxville; University of Michigan; Tokyo University; and University of Mannheim, Germany.
Averant, Inc. reported that Solidify, its functional verification product, has been put into production use by more than 27 companies worldwide. Averant's customers include leading companies designing ICs, ASICs, and FPGAs for telecommunication, networking, and data processing applications, such as Cisco Systems, Compaq Computer, Nvidia, UltimateTV, Lucent, Hitachi and Fujitsu .
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-- Ann Steffora, EDACafe.com Contributing Editor.
