I had a chance to speak by phone with Aki Fujimura on December 10th about the announcement and the X Initiative in general. Fujimura is an X Initiative Steering Group Member and CTO for New Business Incubation at Cadence Design Systems, Inc.

He told me, “This UMC announcement is important, coming on the heels as it does of the announcement from Toshiba last month that they've released functional silicon with X architecture - a block of a particular, highly confidential 90-nanometer chip. One thing that's important to point out here is that not only is Toshiba announcing the world's first 90-nanometer functional test chip using the X architecture, but they've produced it using their regular flows. Toshiba is ready [for X], and now UMC is the first pure-play foundry to be ready as well. [Clearly], the X Initiative will be producing chips in 2004. The X Initiative consortium published a road map in 2001, which said that 2004 would be the year of production. Now it's clear that it will be.”

“People often ask us what kind of chips the X architecture is relevant to in comparison with the conventional Manhattan architecture. Our answer is that anyone who cares about the costs of volume, performance, or power consumption on the chip should care about X architecture, because we can show simultaneous improvements in all 3 of these dimensions. In the consumer space, the volume aspect and lower power are important. For the processor people - microprocessors, processor cores, DSPs, network processors, anything that has processor in the name - those are likely to be the kinds of chips that care about performance and speed. Using the X architecture, these people won't have to [restrict improvements] in just one area, they'll get improvements in all of them.”

“Of course, to the extent that any change in technology is costly, the costs of moving over to the X architecture [from traditional architectures] will have to be justified. But the X architecture has been carefully designed so that it's inherently sideways and backwards compatible with the traditional Manhattan architecture. Data compilers, datapath compilers, existing pieces of IP - these are all completely compatible between Manhattan and X. There's no need to spend any extra energy on new IP at all. Now if you say that you have an ARM core and you're choosing to implement that core in an X architecture, there will of course be some costs there.”

“Why doesn't everyone move over to the X architecture? Well, this is somewhat of a controversial point. I would say that, eventually, everybody should be doing X, but that eventuality will probably not be here until about 2010. First the high-end, sophisticated customers will adopt the technology, and then it will gradually gain wider acceptance.”

“Having said this and given that the current world is both Manhattan and X, what's important to remember is that there are advantages to both. Manhattan's architecture, tools, and methodology are the status quo. People are used to it and there's little resistance to using it. But in places where X shows a particular advantage - and X is very strong in random logic - people are going to make the mental switch over [to the new technology]. Say you've got a million gates or more of random logic, then the X architecture is suitable. If you have less than that and the rest of the chip is dominated by analog or memory or custom structure things, then today there's probably not enough justification to overcome the psychological barrier of changing.”

“Today, the X architecture is enabled by IP uniquely provided by Cadence. If you want to use the X architecture today, you do have to use the Cadence tools. And yes, you're right - if by 2010 there's widespread acceptance, of course Cadence will be in a very strong and unique position at that point. But we have a very open source approach today - there are 39 members who have joined the X initiative consortium so far. Over half of those members are actively engaged in engineering projects to prove that X is viable. And the reason why we've got that level of participation is specifically because we have an open and collaborative approach [to the thing].”

“We think of the X Initiative as one of the first collaborative efforts towards true DFM - design-for-manufacturing - initiatives. X has always provided a strong coupling between manufacturing and design, which is why it is one of the great examples of DFM technology. And one of the things that is always worth repeating is that the X architecture is not solely enabled by innovation in routing. Some people thing the technology is about new routing, but it's really about a whole set of improvements including [developments] in clock timing and power. In order to get all of those improvements, it's not sufficient to just [have improvements] in routing. It's important to do placement and extraction as well. The X architecture is making improvements in all of these areas.”



Newsmakers

Beach Solutions has appointed Duncan Nightingale as its European Strategic Accounts Manager. Nightingale will further develop relationships with the company's major accounts and direct the company's new business drive in Europe. Prior to joining Beach, Nightingale worked for various companies including Verisity, Avanti, Analogy, Vantage and LSI Logic. He holds a BSc in Engineering Science and a Masters degree in VLSI Design & Management Studies from Durham University.

Mentor Graphics Corp. and the Microprocessor Research and Development Center (MPRC) of Peking University in Beijing, China, announced the opening of the first SoC verification training Center in China. The training facility focuses on training both domestic and overseas engineers to resolve the simulation and verification issues associated with ultra large-scale ASIC designs. Recognizing the essential nature of emulation technology in verifying multimillion gate SoC designs, the center is introducing the Mentor Graphics VStationPRO emulator, a product capable of modeling the performance of the largest ASIC designs in real-time. The center is accredited as the only training site in China to provide regular training on emulation technology.

Mentor says that by collaborating with the MPRC on emulation technology, the company continues a long-standing technology relationship with the university. The MPRC has also applied DFT, IC physical verification, FPGA design, and high-speed PCB tools for applications in areas including microprocessor design and verification to hardware and software co-design. Mentor says the VStationPRO is the most advanced ASIC verification technology to be deployed by the center.

Professor Cheng Xu, Director of the MPRC and member of the Integrated Circuit Expert Panel of the National High Technology Development Program (863 Program), is quoted: “The new center for SoC Verification builds upon the past success we've had with products from Mentor Graphics. The Mentor Graphics emulation technology greatly bolsters the domestic capabilities for ASIC verification and through the center we will be able to train world-class engineering talent.”

Nassda Corp. announced that it has been issued a patent - “Transistor Level Circuit Simulator Using Hierarchical Data” (#6,577,992) - by the U.S. Patent and Trademark Office. The company says, “This is the first patent issued to Nassda and relates to the validation of the functionality and performance of microelectronic circuits prior to fabrication. The invention describes how the hierarchical nature of microelectronic circuits may be used to simulate the electrical behavior of very large circuits while minimizing the simulation time and memory required. Consequently, circuit designers can perform full-chip circuit simulations in a reduced amount of time.” The company also announced that its CRITIC product was named one of EDN Magazine's Top 100 Products of the Year, in a special report published in the December 11, 2003 issue.

TransEDA has appointed Jean-Luc Bouvresse as CEO of the company. Previously, Bouvresse - who has 20+ years' experience in the semiconductor industry - served as Vice President and General Manager of Philips Semiconductors, and most recently as COO and Vice President of Sales at Philips' spin-off, Adelante Technologies. He has also served in executive roles at Intel, Apple, and VLSI. TransEDA says that Bouvresse will be responsible for building a profitable organization by merging the technologies of TransEDA and TNI-Valiosys, which will provide tools for customers needing coverage and verification in SoC design.

Marc Frouin, CEO of TNI-Valiosys, the holding company of TransEDA, is quoted in the Press Release: “We are very pleased to welcome Jean-Luc as Chief Executive Officer of TransEDA. Jean-Luc brings the expertise of strong multinational management and business development in the System-on-a-Chip market. He has shown that he can multiply business results several times over, and that he can manage various size organizations from the start-up phase up to over $800 million.”



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-- Peggy Aycinena, EDACafe.com Contributing Editor.