“Right now, we're building partnerships with large companies like Texas Instruments, who licenses a family of our PLLs and DLLs for external and internal ASIC designs. We're also building partnerships with design services firms who are distributing our IP and doing the integration work. Lastly, we're pursuing closer relationships with our fabrication partners so we can improve our circuit technologies to be even more robust and tolerant in silicon. Big company or small - they can all license our timing IP.”

“Most importantly, I think that IP - particularly third-party IP - has gotten a bad rap in the past, so the more press that IP gets the more that people will believe that designs can be reusable, that IP vendors are truly good at what they do. If IP isn't written or talked about, the industry won't grow. IP provided by experts in their field of design is not evolutionary - it can be revolutionary. And it's practical from both a technical and a business point of view to let the experts do the real complex design work. The final transition will be when there is total acceptance that our kind of IP - complex analog and mixed-signal IP - can be licensed and a single piece of IP can work in a range of chip designs. We're on the up-slope of adoption of this kind of technology, but we are moving forward.”



Industry News - Tools and IP

Actel Corp. announced it has enhanced its Libero Integrated Design Environment (IDE) to include Magma Design Automation' PALACE (Physical And Logical Automatic Compilation Engine) physical synthesis tool. Actel's OEM agreement with Magma arranges for PALACE - which Magma says provides an average of 20 percent higher performance for ProASIC Plus FPGAs - to be available from Actel as a standalone tool or bundled with Actel's Libero IDE. Actel also announced that the Silver and Gold Editions of the Libero v5.1 IDE now provide device support for up to 300,000 gates. Saloni Howard-Sarin, Director of Tools Marketing at Actel, is quoted in the Press Release: “Now integrated as part of Actel's development tools portfolio, the PALACE physical synthesis tool from Magma offers a simple interface that requires little user intervention.”

Also from Actel - The company announced the availability of a high-density ceramic column grid array (CCGA) packaging “solution” for the company's radiation-tolerant and military-qualified FPGA devices. Actel says the new packaging technology packs 2.5x the I/O density in 90 percent of the footprint available in Actel's existing packages. The company also says that the CCGA624 package “offers an unparalleled combination of density and reliability with minimal board real estate.” The hermetically sealed CCGA package has been developed for “mission-critical” systems - satellite bus and payload subsystems of commercial and military spacecraft, where high levels of reliability and tolerance to thermal stresses in a small footprint are needed.

Per the Press Release: “An attractive alternative to the ball-grid array, the CCGA package utilizes 624 high-temperature solder columns to create a higher standoff and provide greater tolerance to the stresses caused by different rates of thermal expansion between the PCB and the package. As a result, the thermal fatigue life of the package solder joints is significantly increased. Additionally, the solder columns can be placed as much as 50 percent off the center of the PCB's landing pad and provide sufficient flexibility to realign properly with the pad during solder flow operations.”

Ken O'Neill, Director of Military and Aerospace Product Marketing at Actel, is quoted: “Continuing our heritage as the FPGA leader in the space and military markets, Actel is committed to providing innovative FPGAs and intellectual property cores to the community. In keeping with our legacy, the high-density CCGA packaging solution extends the benefits of our radiation-tolerant and military-qualified FPGA product portfolio to better meet the requirements of applications where tight physical constraints demand the highest levels of integration.”

Agilent Technologies Inc. introduced a new simulation model for high-frequency Gallium Arsenide (GaAs) and Indium Phosphide (InP) heterojunction bipolar transistors (HBTs). The HBT model for Agilent Advanced Design System (ADS) software is designed to provide “greater accuracy and improved convergence over existing HBT models. This helps reduce design turns and shorten the design cycle of high-frequency ICs for applications such as power amplifiers for wireless handsets and wireless local area networks.”

Per the Press Release: “Today, many high-frequency circuits are designed in GaAs or InP HBT processes. Many existing GaAs HBT models use models originally created for silicon bipolar junction transistors (Si BJTs). Using existing Si BJT models to simulate GaAs or InP HBTs for high-frequency IC design contributes to inaccurate and incomplete results for large-signal nonlinear circuit simulations. Agilent's HBT model is designed specifically for GaAs and InP processes used in high-frequency design, and supports both single and double heterojunctions. The new model is based on research originally performed by a working group led by the University of California San Diego (UCSD) for a GaAs physics-based model known as the DARPA/UCSD HBT model.”

Ansoft Corp. released ePhysics, software that the company says expands the capabilities of the Ansoft's HFSS and Maxwell 3D tools. The company also says that with ePhysics, engineers can now incorporate three-dimensional steady-state thermal, transient thermal and linear stress analysis into their existing electromagnetic-based design flows.

Zoltan Cendes, Chairman and CTO at Ansoft, is quoted in the Press Release: “The combination of increasing frequencies and dissipated power, together with reduced size and weight, has made temperature and stress a great concern to electrical/electromagnetic engineers designing present-day electrical devices. Often a product's lifetime and/or performance metric is greatly reduced by excessive temperatures and stresses that result from electromagnetic heating and forces. In other cases, electromagnetic heating and stresses can be harnessed to achieve desired design goals. In either case, ePhysics extends our core experience in electromagnetic analysis to enable electrical/electromagnetic engineers to optimize their designs for maximum performance and cost efficiency.”

BindKey Technologies announced that Tower Semiconductor Ltd. has selected BindKey's RapiDesignClean rules-driven layout “solution” to be part of Tower's standard IC design methodology. BindKey describes RapiDesignClean as “the industry's first rules-driven layout solution for custom design of nanometer ICs.” Tower says it selected RapiDesignClean to support increased demand for engineering resources that is a result of the growing number and complexity of the company's design rules.

Sergio Kusevitzky, Vice President of IP and Design Services for Tower, is quoted in the Press Release: “On its own, RapiDesignClean has increased layout productivity by more than 20 percent. Our engineers can quickly acquire high proficiency in new processes because RapiDesignClean significantly reduces the need to memorize complex rule sets. This provides flexibility in moving engineers between projects, thus optimizing the company's resources. Moreover, we are able to complete designs in a single iteration as RapiDesignClean is applying the same design rules as our sign-off DRC tool.”

Cadence Design Systems, Inc. announced that it has “supported” Motorola in delivering a complex IC design with 62+ million transistors. Cadence says it provided engineering services and a complete back-end design flow at 130 nanometers, and that it helped Motorola “transition from a non-Cadence flow to a completely new methodology based on the Cadence Encounter digital IC design platform.”

The companies say that the new flow is targeted at TSMC's 130-nanometer technology, and that this particular situation allowed Motorola to progress from final netlist to tape-out in six weeks. The end product was the MRC6011, a “highly programmable reconfigurable compute fabric (RCF) device,” which Motorola says combines “system-level flexibility and scalability with the cost-competitive and low-power consumption characteristics of an ASIC-based device.”

Also from Cadence - The company announced that Faraday Technology Corp. has developed a design implementation flow for its Metal Programmable Cell Array (MPCA) structured-ASIC technology, using Cadence's Encounter platform.

The companies say that Cadence is “the first EDA vendor to enable Faraday to conduct actual chip implementation methodology with its structured ASIC paradigm. Faraday's structured ASIC implementation flow was based on Cadence's leading-edge continuous convergence methodology provided by the Cadence Encounter platform. The flow was successfully validated with an actual test chip tape-out in May 2003. The major benefit of the flow is that it helps Faraday engineers drive its customer design netlist from a structured ASIC floorplan specification to a physical design, with fast and guaranteed timing and signal integrity closure.”

From Cadence, as well - The company announced that TSMC has “validated” Cadence's Fire & Ice QXC for the TSMC's Nexsys process, and that Fire & Ice QXC is “an accurate full-chip extractor, tackling in-die process variations inherent in 90-nanometer design. With new-generation 3-D models, Fire & Ice QXC correctly accounts for all copper and optical effects, enabling designers to reduce timing margins and improve the performance and yield of their designs.”



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-- Peggy Aycinena, EDACafe.com Contributing Editor.