Twentieth Anniversary Celebration and Expanded Technical Track Program Were among the Highlights at EDA's Largest Users Group

MOUNTAIN VIEW, Calif., April 12 — (PRNewswire) — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the Best Paper Awards for the twentieth annual Synopsys Users' Group (SNUG®) San Jose conference, held in Santa Clara, Calif. on March 29-31. First place was awarded to Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee and Bruce Doyle of AMD and Zhi-Yuan Wu of GLOBALFOUNDRIES for "Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design"; Alvin Loke won the Best First-time Presenter Award for presenting this paper. Second place was awarded to Gerard M. Blair of LSI Corporation for "Hold is not setup (derate is not OCV)." Third place was awarded to Paul Zimmer of Zimmer Design Systems for "'There's a better way to do it!' - Simple DC/PT Tricks That Can Change Your Life."

The SNUG Technical Committee Award went to Avishek Panigrahi and Arvind Parihar of MIPS Technologies, Inc. for "Clock Power Reduction-Analysis Metrics and Power Reduction Techniques." The Technical Committee Honorable Mention Awards went to Krishna Vittala of Microchip Technology Inc. for "Reusable UPF for Multi-Voltage Designs & Handling Analog Macros in Power Subsystems," and to Asif Jafri with Verilab Inc. for "Interoperable Testbenches using VMM TLM."

SNUG San Jose is part of the largest user conference program in electronic design automation (EDA). In 2009, the program attracted more than 7,000 integrated circuit (IC) and system design engineers to open forums in the U.S., India, Taiwan, Singapore, Europe, Israel, China and Japan. Attendees represent the world's largest semiconductor design and manufacturing companies as well as many innovative start-ups.

More than 2,000 technical users attended this year's San Jose event, which marked twenty years of close, continued collaboration between Synopsys and its users. The milestone event included a number of highlights, including the participation of industry luminaries Doug Grose (GLOBALFOUNDRIES), Rick Cassidy (TSMC) and Moshe Gavrielov (Xilinx) who shared their latest perspectives on the evolving industry. For the first time this year, technology tracks for system-level design and compute infrastructure were offered, allowing users access to an expanded program of technology tracks. SNUG San Jose 2010 also marked the first Designer Community Expo, which showcased the integration between Synopsys and more than 50 of its partners from across the electronics industry who provide solutions that address the difficult design challenges SNUG attendees face.

"SNUG was established with a mission to create a rich channel of communication for users to interact with each other and with Synopsys. Twenty years later, that mission hasn't changed," said John Busco, Design Implementation manager, NVIDIA, and SNUG San Jose Technical Chair. "Countless papers, presentations and reunions through the years have brought shared learning and enrichment to thousands of engineers seeking an environment full of technical facts and ideas to help them better address the growing challenges of electronic design, verification and manufacturing. As a user, I look forward to many more years of shared experience through SNUG conferences."

Aart de Geus, chairman and chief executive officer at Synopsys, opened the conference with a keynote sharing his perspective on some important trends. de Geus highlighted SNUG San Jose's 20th anniversary as a testament to EDA's growth and endurance as a highly collaborative, forward-thinking industry. He also spoke about a number of Synopsys' exciting technology developments including Design Compiler® 2010, which is the latest RTL synthesis innovation within the Galaxy™ Implementation platform, as well as the company's expanded activities in the system-level design space with the recent VaST and CoWare acquisitions.

"SNUG's continued evolution has been integral to its longevity as a forum for designers to collaborate with Synopsys and each other," said de Geus. "I am grateful for these opportunities to meet with and learn from our users. I'm always impressed by the wonderful ideas shared at SNUG and the quality of papers submitted. This shared vision helps Synopsys continuously expand our portfolio to address the latest design challenges."

SNUG San Jose 2010 sponsors include: Platinum Sponsors ARM, GLOBALFOUNDRIES, IBM, Samsung Electronics Co., Ltd. and TSMC; Gold Sponsors Altera Corporation, HP, Virage Logic, Xilinx and Zuken; and Silver Sponsors Agilent Technologies and Doulos. The three-day SNUG San Jose conference featured a technical program with 85 presentations, including 36 user papers and 43 Synopsys technical sessions. The presentations focused on challenges that engineers face today in all areas of design, including synthesis, verification, low power design, physical design/sign off, analog/mixed-signal design, custom design, test, IP, embedded software development, rapid prototyping tools and compute infrastructure.

Please visit the Synopsys Users Group website at http://www.snug-universal.org for more information on upcoming events and how to submit a paper for consideration by the SNUG technical committee. Customers can also access proceedings and the award-winning papers at this link.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys, Design Compiler, Galaxy and SNUG are registered trademarks or trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

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