WHAT:
Attendees of this free, day-long event can learn from experts at Cadence and other leading companies about the latest trends and methodologies for tackling low-power design challenges, from functional verification to physical implementation and signoff.
Agenda topics include:
- Vertically integrated designs for energy-efficient SoCs
- Bluetooth Smart and low-power innovation
- Challenges developing sub-volt IP designs for Internet of Things (IoT) applications
- Thriving in a multi-vendor, interoperable, IEEE 1801 low-power design flow
- Panel highlighting the latest trends and challenges in low-power design
Visit the complete agenda and register to attend at www.cadence.com/news/lpsummit.
WHEN:
The Low-Power Technology Summit is scheduled from 9:30 a.m. to 5:30 p.m. on November 18, 2014.
WHERE:
Cadence Design Systems, Building 10 Auditorium
2655 Seely Avenue
San Jose, CA
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at
http://www.cadence.com/.
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact
Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
SOURCE Cadence Design Systems, Inc.
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