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-> Virage Logic
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"Live Demo of DDR3 IP in 65nm"
VirageLogic at DesignCon
1,502
views
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"Optimized MIPI Application Demo",
Hezi Saar
Virage Logic
Views: 1672
"Demo of SiPRO PCIe PHY"
VirageLogic
Views: 1943
"Live Demo of DDR3 IP in 65nm"
VirageLogic at DesignCon
Views: 1501
"Logic NVM for Digital Rights Managment (DRM)",
Craig Zajac
Virage Logic
Views: 1929
"DDR All-Digital PHY+DLL",
Luigi Ternullo
Virage Logic
Views: 3523
"Logic NVM for Wireless Applications",
Craig Zajac
Virage Logic
Views: 7918
"DDR High Speed Interfaces for Increasing Performance and Reducing Power",
Luigi Ternullo
Virage Logic
Views: 1981
"Avoiding Test Escapes to Achieve Near-Zero Defects",
Manish Bhatia
Virage Logic
Views: 2654
"Addressing DDR System Level Concerns",
Luigi Ternullo
Virage Logic
Views: 2280
"Standard Cell Logic Libraries for Demanding Speed Requirements",
Ken Brock
Virage Logic
Views: 3355
"Design Challenges at 32nm and Beyond Technology Nodes",
Vipin Tiwari
Virage Logic
Views: 4647
"Highly Configurable Memory for Advanced Power Management",
Lisa Minwell
Virage Logic
Views: 2846
"NVM for Power Management",
Craig Zajac
Virage Logic
Views: 2338
"DDR High-Speed Interface Solutions",
Luigi Ternullo
Virage Logic
Views: 1985
Total : 14
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