New Technologies in V14 Webinar Series Concludes With Phased-Array Design Flow for 5G and Radar Applications

CEA-Leti Extends 300mm Wafer Line & Adds Avenues for Developing Discruptive Memory, Photonics, 3D and Quantum Technologies

Perforce and Methodics Deliver Fully Integrated Solution For Highly Scalable Semiconductor Design and Embedded Systems Development

Cadence’s John Wall to Present at Nasdaq 39th Investor Conference in London

North American PCB Sales Growth Continues but at a Slower Pace

Hardent & Willamette HDL Named by Breker Verification Systems As Portable Test & Stimulus Standard (PSS) Training Provider For Trek5 Tool Suite

Juliano Mologni, Lead Product Manager ANSYS

Roger Levinson, COO BrainChip

Piyush Sevalia, Executive VP SiTime

EDACafe Editorial by Roberto Frazzoli Samsung Foundry’s roadmap; AI EDA startups; 100x CPU performance boost; new ECC method

EDACafe Editorial by Sanjay Gangal Innovating PCB Design: An Interview with Duncan Haldane, CEO of JITX

Industry Predictions by Sanjay Gangal A New Era for Electric Vehicles: Silicon Mobility and Intel Lead the Charge

Guest Blogger by Sanjay Gangal Streamline 3D IC verification with a shift-left strategy

Siemens EDA by Vijay Chobisa The Rise of Custom Acceleration

Senior DPU System Application Engineer for Nvidia at Santa Clara, California

Design Verification Engineer for Blockwork IT at Milpitas, California

Senior Hardware Engineer IV – CA for Ampex Data Systems Corporation at Hayward, California

Hardware Engineer for PTEC Solutions at Fremont, California

Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California

SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024

IEMI 2024- Integrated Electronics Manufacturing & Interconnections (IEMI) at Bengaluru India - Jul 29 - 30, 2024

Flash Memory 2024 Conference & Expo FMS2024 at Santa Clara Convention Center Santa Clara CA - Aug 6 - 8, 2024

SEMICON Taiwan 2024 at Taipei Nangang Exhibition Center Taipei Taiwan - Sep 4 - 6, 2024