Extreme DA Granted Patent for Statistical Timing Optimization of Digital Circuits

Santa Clara, Calif. –– March 9, 2009 –– Extreme DA™, the leader in new-generation timing analysis software, announced it has been issued a patent by the United States Patent and Trademark Office for its method of statistical timing optimization of digital circuits.  The patent, #7,487,486, covers technology used for improvement of design performance and reduction in power consumption and die-size of digital IC designs produced in 65nm processes and below.

As IC technologies are scaled to finer feature sizes, it becomes increasingly difficult to control process and parameter variations. The increasing fluctuations in manufacturing processes cause uncertainties in circuit behavior, and significantly impact the circuit performance and product yield. The problem is made worse by the growing sensitivity of current designs to environmental fluctuations, such as variations in temperature and voltage supply. Current design methodologies fail to address the nanometer-scale manufacturing and design realities; specifically, how to consider large-scale variations at all levels of the design creation hierarchy.

In nominal timing analysis, critical path and slack are two important concepts that have been widely utilized for timing optimization, but the impact of large-scale process variations renders these concepts obsolete and invalid.  The method of this new patent addresses the critical need for a new methodology for using statistical timing analysis results to guide timing optimization, as well as to explore the tradeoff between performance, power consumption, yield and cost. 

"This patent forms the basis for a new innovative approach to statistical timing analysis," said Mustafa Celik, CEO. "It describes the next-generation capability needed for the complex nanometer designs which chipmakers face today. For leading-edge digital ASIC designers, they can no longer rely on traditional timing validation methods to improve designs.  We believe our innovative statistical timing analysis in GoldTime delivers a new level of accuracy and robustness for optimizing ICs performance and yield."


About GoldTime — The New Standard in Sign-off Timing
GoldTime by Extreme DA, is the new-generation timing analysis technology that delivers 5X better speed and capacity. With its new from-the-ground-up architecture, designers can sign-off with certainty and achieve faster timing closure. Whether verifying a current generation design across corners or doing a statistical analysis to optimize the performance, power and yield for 40nm ICs, GoldTime delivers the answers while the competition is still figuring out the results.

About Extreme DA
Headquartered in Santa Clara, Calif., venture-funded Extreme DA develops and licenses software products that provide sign-off analysis and improve the performance and yield of nanometer integrated circuits prior to manufacture.  The company’s investors include Foundation Capital, IT-Farm Corporation, and Lanza techVentures.  For the latest news and information on Extreme DA, visit www.extreme-da.com or write to info@extreme-da.com.

--end--

Extreme DA, the Extreme DA logo, and Extreme DA GoldTime are trademarks of Extreme DA.  All other legal marks are the property of their respective owners.

Contact :
Jean Armstrong, PR Counsel for Extreme DA        Ruben Molina, Dir. of Technical Marketing
Armstrong and Associates, Inc.                   Extreme DA
jean@aaa-pr.com,  503-477-5434                   408-588-1112, x.32

Featured Video
Latest Blog Posts
Vijay ChobisaSiemens EDA
by Vijay Chobisa
The Rise of Custom Acceleration
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Nomination Deadline for Phil Kaufman Award and Hall of Fame: June 30
Jobs
Hardware Engineer for PTEC Solutions at Fremont, California
Senior DPU System Application Engineer for Nvidia at Santa Clara, California
Senior Hardware Engineer IV – CA for Ampex Data Systems Corporation at Hayward, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Post Silicon Hardware Engineer for Nvidia at Santa Clara, California
Upcoming Events
SemiconWest - 2024 at Moscone Center San Francisco CA - Jul 9 - 11, 2024
Flash Memory 2024 Conference & Expo FMS2024 at Santa Clara Convention Center Santa Clara CA - Aug 6 - 8, 2024
SEMICON Taiwan 2024 at Taipei Nangang Exhibition Center Taipei Taiwan - Sep 4 - 6, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise