Videos -> General


SuperGuard Library Safety Qualification Suite - Solid Sands
Solid Sands
 		1,988 views
«Prev Next»
Keywords: C++ Compiler Testing, Library Safety Qualification, SuperGuard Suite, Safety-Critical Software, ISO C Language Compliance, Traceability in Software Libraries
Description: The SuperGuard Library Safety Qualification Suite is a requirements-based test suite for the C and C++ standard library with full More »

View SuperGuard Library Safety Qualification Suite - Solid Sands Views: 1987 View SuperTest Compiler Test and Validation Suite - Solid Sands Views: 2527 View IPC 2024 Registration is Now Open! Views: 307

View ECO challenges at advanced nodesAvidan Views: 2067 View True Circuits Presentation at DAC 2019 Views: 483 View True Circuits at DAC 2018, featuring John Maneatis Views: 433

View Intel Unleashed: Engineering the Future (Event Replay) Views: 2047 View Register Today for Simulation World 2021 | April 20 & 21 Views: 1075 View IPC APEX EXPO 2021 is the place to be...from wherever you are! Views: 653

View From Sand to Silicon: The Making of a Microchip | Intel Views: 758 View How Intel Makes Chips: Concept to Customer Views: 747 View IPC APEX EXPO 2020 Views: 551

View Don't Have DAC FOMO, Submit Your Work to the Designer, Embedded Systems or IP Track Views: 875 View PolarFire SoC FPGA Brings Real-Time to Linux Views: 2396 View Deep Learning with VGG16 Neural Network Demo on DesignWare EV6x Vision Processor Views: 1359

View People distance measurement with Tara - Stereo camera Views: 2354 View 5MP AutoFocus HD UVC USB Board Camera Views: 2351 View Point Cloud Demo with Tara - Stereo vision USB 3.0 camera Views: 1987

View Paripath Technology Views: 1766 View ZofzPCB Cross-Section feature Views: 1337 View How to create innovative architecture using VisualSim? Views: 844

View Why do we need system-level design for electronics and embedded systems? Views: 758 View Architectural tricks to maximize memory bandwidth Views: 1928 View Designing a Multimedia SoC using system-level simulation Views: 1097

View OrCad to ZofzPCB Views: 880 View High Level Synthesis Design Space Exploration Views: 908 View SystemC part1 Views: 899

View GSA Panel: IP Integration with ASIC Technology Views: 1335 View DFMStream Overview Views: 879 View Using templates in BluePrint PCB Views: 1099

View Downstream BluePrint Overview Views: 1032 View ZofzPCB: FREE 3D Gerber Viewer. Views: 1716 View Xilinx and Open-Silicon HMC Memory Solution Views: 885

View Introduction to Power Electronics Views: 1105 View SSD & Memory: Why It Matters What You Choose Views: 758 View MemoryMirror* First Body-Controlled Smart Mirror Views: 1219

View EDA Playground Introduction Views: 1813 View Sundar Iyer, CEO Views: 2806 View 10GBASE-KR Electrical Conformance with Virtex®-7 FPGAs Views: 2346

View Introduction to JasperGold Low Power Verification App Views: 2236 View Vivado HLS Technical Introduction Views: 1859 View EMC simulation consumer electronic devices Views: 2150

View iPhone 5S Teardown Round Up Views: 1157 View Combined 3D electromagnetic and spin response simulation of MRI systems Views: 2342 View Using IP/SoC Executable Specifications and Integration with Formal Verification Views: 1607

View Tandem Configuration for 7 Series Views: 1293 View Hardware/Software Cross-Trigger for Embedded Design Views: 1597 View Heterogeneous Multicore Debugging with Xilinx SDK Views: 1783

View Agilent Genesys Filter Synthesis Tools Views: 1666 View Two Reasons Why Auto-Adaptive Equalization is Critical to Transceiver Design Views: 1558 View Multiphysics Approach for a Magnetron and Microwave Oven Design Views: 1673

View Understanding Vivado Plug and Play IP Views: 1616 View Vivado XDC Macro Creation Views: 1964 View Using the Xilinx Power Estimator Views: 1574

View Using Vivado Serial IO Analyzer Views: 2018 View Using Tcl Scripts as Constraint Files in Vivado Views: 2256 View Analyzing Device Resource Statistics in Vivado Views: 1358

View Compilation Units in Vivado Synthesis Views: 1479 View Creating and Analyzing Multi Emitter Environment Test Signals with COTS Equipment Views: 1566 View How to Make Your Existing Designs More Robust Views: 1283

View Breaking the RF Carrier Barrier 0 to 200 in Under a Second Views: 1391 View Advances in Load Pull Simulation Views: 1690 View 4 Steps to Bring Up a CFP2 Optical Module with a Virtex-7 HT FPGA Views: 1846

View TSV and Interposer modeling, design and characterization Views: 1937 View Xilinx UltraScale™ Architecture -- Industry's first ASIC-class All Programmable Architecture Views: 2219 View Genesys Overview Views: 1407

View Intel® Xeon Phi™ coprocessor Views: 2470 View Andrew McAfee: What will future jobs look like? Views: 2056 View Rambus Inventor Profile - Elke DeMulder Views: 1571

View Research@Intel 2013: Intelligent Everything Views: 1526 View Human-Centered Design Views: 1479 View Rambus Inventor Profile - Christophe Chevallier Views: 1419

View Rodney Brooks: Why we will rely on robots Views: 2432 View Research@Intel 2013: Opening Keynote Views: 1633 View 5.23.13 15th Annual Top 10 Tech Trends Views: 1442

View NVIDIA GRID vGPU Technology Unveiled at Citrix Synergy Views: 1569 View Keith Barry: Brain magic Views: 1884 View Nanomaterials: The Science of the Small: Stefan Bon at TEDxWarwick 2013 Views: 2424

View Modeling Next-Generation Applications with Intel® CoFluent™ Studio Views: 2535 View Keller Rinaudo: A mini robot -- powered by your phone Views: 1823 View First Look: Industry's First 20nm FPGA Transceiver Views: 1496

View CR-8000 - Intelligent Engineering Views: 1983 View Introducing Samsung GALAXY S4 Views: 1682 View IESA Vision Summit 2013 Views: 1948

View Accelerating DSP Design Productivity with All Programmable FPGAs and SOCs Views: 1378 View Samsung Unveils Galaxy S4 Views: 1908 View Altera to Build Next-Generation, High-Performance FPGAs on Intel's 14 nm Tri-Gate Technology Views: 1939

View Accelerating DSP Design Productivity with All Programmable FPGAs and SOCs Views: 1293 View VHDL-AMS inverting op-amp design & simulation in ViaDesigner Views: 2933 View Reid Wender, VP Marketing Views: 2260

View Keynote By Dr. Ajoy Bose : SoC Realization – Building a Bridge to New Markets and Renewed Growth Part 1 Views: 2950 View Keynote By Dr. Ajoy Bose : SoC Realization – Building a Bridge to New Markets and Renewed Growth Part 2 Views: 3172 View Keynote speech by Jim Hogan: Making Money from SoC Realization – where are we today? Part 1 Views: 3037

View Keynote speech by Jim Hogan: Making Money from SoC Realization – where are we today? Part 2 Views: 2992 View Marcelo Lubaszewski Views: 2047 View Rick Carlson, Vice President - Sales Views: 1682

View "A World of Semiconductor Solutions Down to 14nm",Bob Durstenfeld Views: 3716 View "Challenges for Digital Timing Sign-off at the 20nm Node", Ruben Molina, Magma Views: 2506 View "ECAD and MCAD Solutions", Manny Marcano, President and CEO Views: 3996

View Pantheon 7: Complex Design Just Got Simpler Views: 1688 View Interview with Aart de Geus Views: 1503 View Dieter Therssen & Jane Judge Views: 1951

View Interview with Tom Pennino: Working with Pat Pistilli Views: 2614 View "Free Mar. 16 Design Education Conference", Ali Iranmanesh Views: 2653 View Interviews with MP Associates Staff Views: 3033

View Interview with Pat Pistilli's Daughters Views: 3942 View NanoCMOS Statistical Variability and Reliability, Dr. Asen Asenov Views: 4157 View EDAC Congratulates Pat Pistilli, 2010 Phil Kaufman Award Recipient Views: 2184

View Why DAC 2010? Views: 3276 View Jim McCanny at Japan EDSFair 2009 Views: 2983 View Mark Gogolewski MEMCON 2009 Keynote Clip Views: 8335

View Exceed Connectivity Solution, Views: 3363 View "Make or Break Year" Views: 8865 View Movie: EDA - Where Electronics Begins Views: 4470

View Preview: EDA - Where Electronics Begins Views: 3612
Total : 115
Featured Video







Submit | More Videos 
Sponsored Videos
Submit | More Videos 
Editorial
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
Intel CEO retires; new U.S. restrictions on exports to China; HBM’s growing importance
More Editorial  
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
The Evolution of the Semiconductor IP Market
Sanjay GangalEDACafe Editorial
by Sanjay Gangal
NVIDIA and Industry Leaders Unveil Groundbreaking Real-Time Digital Twin Technology
Sanjay GangalSiemens EDA
by Sanjay Gangal
Enhance power reliability through design-stage layout optimization
Sanjay GangalIndustry Predictions
by Sanjay Gangal
Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites
More EDA Blogs 
Jobs
CAD Engineer for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Submit Resume | Post Jobs | More Jobs 
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025
DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025
Submit | More Events 



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise