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Architectural tricks to maximize memory bandwidth
Mirabilis Design Inc
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1,931 views |
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| Keywords: memory bandwidth, memory controller, performance analysis, architecture exploration, AXI, ARM, DDR4, video processing, pipeline |
| Description: Unexplained Read/Write latency can be attributed to- cache hit-ratio, burst length, commands-in-a-row, AXI Bus arbitration, and video More » |
| Description: Unexplained Read/Write latency can be attributed to- cache hit-ratio, burst length, commands-in-a-row, AXI Bus arbitration, and video pipeline. During this Webinar, we will present the system-level modeling of complex video pipelines and their interface to memory using a Network of Buses. With this model, we shall optimize the address allocation to IP blocks, burst lengths and memory controller settings to get close to 98% efficiency. « Less |
