Description: The need to meet the ever-shorter time-to-market window, as well as the need to focus on core competence, has led to a steep increase in the adoption and integration of 3rd party Semiconductor IP (SIP) to meet today's SoC development challenges. While the adoption of SIP increases productively and enables innovation, it also introduces new challenges for interface specification, integration and verification on a large scale.
This video showcases the combined solutions from Duolog and Jasper that alleviate the time-consuming and error-prone tasks associated with SIP-based SoC integration and verification. The collective Duolog and Jasper flow enables design teams to quickly and accurately detect issues, inconsistencies and omission when assembling complex SIP-based systems. The integrated design flows enable designers to work from black-box system specifications, through design capture and assembly, to verification. Development teams can verify the correctness of both the specification and the implementation, while also detecting exclusions in the specification. « Less |
