Videos -> DAC 2011


Loading the player ...
 "Conformal ECO Designer Automates Frontend Changes",
Kenneth Chang
Cadence
 		2,060 views
«Prev Next»

View "New Conversation Central on Facebook", Karen Bartleson Views: 1703 View Aceplorer ESL Power Exploration and New Silicon Valley Office", Ghislain Kaiser Views: 2658 View "New SOS Data Management Integrations and Visual Design Diff Update", Karim Khalfan Views: 2531

View "New Formal Verification Methodology and Custom Modeling Service", Vigyan Singhal Views: 4220 View "New Visual Verification Suite", Ellis Smith Views: 1442 View "New Soft IP Tagging", Kathy Werner Views: 2517

View "New TotalHistory Debugging for Rapid Prototyping ", Shyam Uma Chander Views: 4220 View "New ProtoLink Probe Visualizer, UVM Support and Certitude Update", Howard Mao Views: 2610 View "Socrates Suite of IP Integration Tools", Norman Walsh Views: 2050

View "Launching Nimbic, B Round Funding, nCloud and nWave", Raul Camposano Views: 1559 View "New UVM 1.1 Standard and Upcoming Unified Coverage Standard", Dennis Brophy Views: 2280 View "Chip Timer Optimizes Designs", Mehmet Cirit Views: 2035

View "New PCIe UVM Verification IP and UVM Tips", Craig Stoops Views: 5330 View "New 28nm FLows, 3DIC, Calibre RealTime," Michael Buehler-Garcia Views: 4240 View "My 40nm Design Closure Experience with Cadence Conformal ECO", Sid Allman, H/W Design Mgr. Views: 3122

View "Outsourcing N-1 Designs", Dilip Lalwani Views: 2061 View "New All-in-One Tekton SPX Sign-off Platform", Ruben Molina Views: 1947 View "New FastSpice, MEMs + ASICs, Designer Productivity", John Zuk Views: 2761

View "New Sillicon One Initiative", Behrooz Zahiri Views: 1815 View "New Sorcery CodeBench for Embedded Systems", Glenn Perry Views: 2812 View "New Cloud-based FPGA Design Development", HarnHua Ng Views: 2045

View "Design Script Management and Development", Rosesmary Francis Views: 1398 View "Place-n-Route: New Parametric OCV and Adaptive Multi-mode/Multi-corner", Eric Thune Views: 2926 View "Artisan Physical IP Update", John Heinlein Views: 1373

View "TSMC AMS Ref. Flow 2.0 and Tanner Suite Integration", Ravi Subrmanian Views: 4203 View "New OlympusSoC Floorplanning and Partitioning", Pravin Madhani Views: 2308 View "Whole Product Development and Management", Rick Stanton Views: 1276

View "Vertical Solutions", Lauro Rizzatti Views: 1896 View "Conformal ECO Designer Automates Frontend Changes", Kenneth Chang Views: 2059 View "Virtual Prototyping and System Optimization", Johannes Stahl Views: 1382

View "Power Management from Front to Back", Vic Kulkarni Views: 2588 View "TSMC Partnership, System Development Suite and 20nm", John Bruggeman Views: 1529 View "New AMBA 4 Hardware Coherency Spec", Mike Dimelow Views: 1405

View "Design Quality Measurement and Closure", Francois Constant Views: 1418 View "New DFM Services for Yield for 40nm and 28nm", Manoj Chacko Views: 1682 View "28nm Design Creation", Wei Lii Tan Views: 1987

View "IP Reuse and the Global Design Platform", Shiv Sikand Views: 2388 View "3D TSV and Silicon Test", Steve Pateras Views: 6684 View "Suprising Verification Research Results", Harry Foster Views: 3450

View "Analog System Simulation and Sign-off", Andrew Betts Views: 4251 View "Lynx Design System Update: ARC Cores and IDT Usage", Neel Desai Views: 1519 View "New Perl Scripting Front-End", Rob Dekker Views: 5958

View "ARC Processor Update", Mike Thompson Views: 1854
Total : 43
Featured Video







Submit | More Videos 
Sponsored Videos
Submit | More Videos 
Editorial
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
Nvidia-powered CAE acceleration; new Keysight EDA software; CoWoS roadmap; new datacenter inference solution
More Editorial  
Latest Blog Posts
Paul CohenBridging the Frontier
by Paul Cohen
Honoring Dr. Jason Cong During the Phil Kaufman Award Ceremony and Banquet
Sanjay GangalIndustry Predictions
by Sanjay Gangal
Intel’s New Xeon 6 SoC Redefines vRAN Efficiency, Single-Server Footprint for Cell Sites
Sanjay GangalEDACafe Editorial
by Sanjay Gangal
Siemens’ Innexis Suite Advances Shift Left for Faster, Earlier IC Development
Romain PetitSiemens EDA
by Romain Petit
Multi-FPGA Partitioning – What’s the Recipe for Success?
More EDA Blogs 
Jobs
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Submit Resume | Post Jobs | More Jobs 
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025
DATE 2025 - Design, Automation and Test in Europe Conference at France - Mar 31 - 2, 2025
Submit | More Events 



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise