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Chip/Package/Board: Constraint Driven Co--Design
CST
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| Keywords: CST, Chip, Board, Package, Co-Design, Constraints |
| Description: Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. More » |
Description: Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.
This webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling.
Difference between segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed and based on the results, guidelines are outlined. « Less |
