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Riviera-PRO™ Overview: Advanced Verification Platform Aldec
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Keywords: ASIC, FPGA, SOC, Simulation, Co-Simulation, Verification, Validation, Debugging, Mixed-Language, HDL, VHDL, Verilog, SystemVerilog, SystemC, Aldec, Riviera-PRO |
Description: Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables More » |
Description: Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. « Less |
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