Description: Watch in this video examples of how to use DS-5 unique FPGA-adaptive capabilities to debug your system across CPU and FPGA domains. Here DS-5 Altera Edition, part of Altera® SoC EDS toolkit, and Quartus are used simultaneously to connect to a Dual-core ARM Cortex®-A9 Altera Cyclone V SoC board via Altera USB Blaster II to enable software-hardware co-development.
Use the DS-5 Debugger to view the content of custom hardware (FPGA) registers at any point when you halt the CPU. Then learn how to use Signal Tap II and DS-5 to setup system-wide break conditions, which can be used to stop the CPUs when a specific signal on the FPGA side transitions from high to low, for instance. Then visualize the status of both software and hardware using the two tools simultaneously. Finally, see how the CoreSight™ System Trace Macrocell (STM) can be used as a powerful instrumentation tool to bring together hardware and software worlds, simplifying your development process. « Less |
