Very Deep Submicron Layout (VDSL)
The VDSL course is targeted towards developing the skills necessary to understand the challanges faced by physical engineers in completing layouts at deep submicron levels and provides practical real life solutions.
LEARNING OUTCOMES:
Layout of VDSL circuits on CMOS processes,
Understanding the impact layout has on yield and discuss how yield is no longer just a foundry responsibility,
Understanding the parasitics elements introduced by the VDSL process.
SYLLABUS CONTENT
CMOS Scaling Implications,
Yield,
Interconnect Parasitics,
Device Parasitics,
Matching,
Isolation Strategies,
Design for Manufacture.
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