Custom Digital Layout Techniques
The Custom Digital layout Techniques course focuses on techniques used in the physical design of standard cells, and full custom digital blocks. Starting with the layout of basic MOS transistors, the course develops to cover the more advanced techniques used in creating area efficient full custom digital layouts.
LEARNING OUTCOMES:
Familiarity with the concepts of CMOS logic processes,
Layout of digital cells,
Silicon area reduction techniques,
Understanding of custom digital floorplanning methodologies,
SYLLABUS CONTENT:
CMOS Logic process overview,
MOS transistor layout,
Silicon area reduction techniques,
Floorplanning methodologies and techniques,
Common custom digital layout techniques,
Power routing strategies.
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