All Categories : EDA Tutorials Bookmark and Share

Title : MT-024: ADC Architectures V: Pipelined Subranging ADCs
Company :
Date : 25-Mar-2009
Rating :
Downloads : 52

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

The pipelined subranging ADC architecture dominates today's applications where sampling rates of greater than 5 MSPS to 10 MSPS are required. Although the flash (all-parallel) architecture (see Tutorial MT-020) dominated the 8-bit video IC ADC market in the 1980s and early 1990s, the pipelined architecture has largely replaced the flash ADC in modern applications. There are a small number of high power Gallium Arsenide (GaAs) flash converters with sampling rates greater than 1 GHz, but resolution is limited to 6 or 8 bits. However, the flash converter still remains a popular building block for higher resolution pipelined ADCs.
User Reviews More Reviews Review This File
Featured Video
Jobs
Design Verification Engineer for Blockwork IT at Milpitas, California
CAD Engineer for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise