In terms of course prerequisites, I am assuming that everybody is already familiar with RTL-level VHDL via the Digital System Design course (ECE 4743/6743) or some other source. This object of this course is to introduce the student to more of the VHDL modeling language than what has been covered in previous courses. We will also cover aspects of Verilog which do not overlap VHDL functionality, and look at mixed-mode simulation.
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