Mirror-Box™ to be formally announced and demonstrated in Booth #204 at EDSFair in Japan
Tokyo, Japan – January 27, 2011 – Aldec Inc., a pioneer in mixed HDL language simulation and hardware-based assisted verification solutions for FPGA and ASIC designs, announces the release of a new debugging technology called Mirror-Box™ to the HES™ platform.
“As a technology-leader in the electronic design verification industry, Aldec is committed to meeting the growing needs of verification engineers by adding new debugging technologies like Mirror-Box. The ability for engineers to quickly validate and compare differences between simulation model and actual hardware without rerunning Synthesis and P&R increases their overall productivity in debugging.” said Dave Rinehart, Vice President of Aldec, Inc.
Mirror-Box™ Debugging Technology
As designs become more complex and chip density grows, functional verification becomes increasingly overwhelming and time-consuming. To help verification engineers reduce their verification cycles, and in order to meet tight time-to-market deadlines, Aldec adds the Mirror-Box debugging technology to streamline debugging during hardware-assisted simulation. The Mirror-Box technology allows any component, at any hierarchical level, to be mirrored such that two implementations of the same component can be simulated: one implementation is the original RTL code which resides in the HDL Simulator and the other is its FPGA counterpart which resides in the hardware board.
Mirror-Box Benefits:
- Time Savings - Verification engineer can switch between RTL code and FPGA hardware models without having to rerun Synthesis and Place and Route. This eliminates the need to rebuild the FPGA several times during debugging, which ultimately helps in detecting more errors and bugs per day.
- In-Hardware Validation - Runtime comparison of component outputs between RTL code and actual hardware, allowing detection of discrepancies between the simulation model and real hardware.
- Flexibility - Verification engineer can make changes to the design component selected as Mirror-Box in HDL simulator while the rest of the design runs in the FPGA hardware.
For more information, including white papers and webinars, visit www.aldec.com/products/HES.
About HES™
HES is a patented hardware-based verification system for large and complex SoC designs. HES is also a versatile unified platform that enables simulation acceleration, SoC emulation, HW/SW co-verification, software validation, ESL co-simulation and prototyping. HES includes Transaction Level Modeling (TLM) with SCE-MI 2.0 for high-performance emulation using Aldec, Dini Group®, Synopsys® HAPS™ or in-house FPGA prototyping boards up to 37 Million ASIC gates.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
www.aldec.com
HES, DVM, Riviera-PRO, Active-HDL and Aldec are trademarks of Aldec, Inc.
All other trademarks or registered trademarks are property of their respective owners.
Media Contact:
Christina Toole
Marketing Manager
Aldec, Inc.
+(702) 990-4400
Email Contact Email Contact Email Contact Email Contact Email Contact