As geometries continue to shrink, the complexity of hierarchical design is growing dramatically. Today’s hierarchical tools are very difficult to use because they are all created by adding some extra hierarchical data structures on top of a place-and-route tool that can only work on a flat data model. The results are very poorly integrated systems with a lot of unnecessary overhead and complex flows. Since the core engines of Aprisa (ATopTech’s leading physical design solution) work directly on an integrated hierarchical data model, Apogee is essentially a natural extension of Aprisa, which allows users to perform the hierarchical place-and-route tasks as easily as running a flat place-and-route task.
The Apogee solution includes the two key functions in hierarchical design: top-down chip planning and partitioning, and bottom-up chip assembly and chip-level timing closure. These functions of Apogee are tightly integrated with Aprisa, so the user can easily manage hierarchical data and also switch between top-level design and block-level design seamlessly.
For top-down chip planning and partition, Apogee utilizes the award-winning place-and-route engines from Aprisa to achieve a high-quality partition generation, pin assignment, and feed-through insertion, enabling the user to create hierarchical designs with much better quality and unprecedented speed.
For bottom-up chip assembly and closure, Apogee makes it possible for designers to do full-chip timing analysis with automatically generated timing-accurate models for the blocks, with very fast run times. Apogee also allows the user to work on individual blocks with the full-chip timing picture and fix the top-level timing issues. This addresses one of the most challenging issues of today's hierarchical designs because the size of the design can easily exceed the capacity of timer and physical implementation tools.
“Apogee has already seen several successful tape-outs from a major fabless semiconductor company, proving it is ready for deployment,” said Dr. Ping-San Tzeng, ATopTech President and CTO. “We listened to our customers about the challenges and frustrations they had at the top level, and set out to solve those issues. The addition of Apogee to our portfolio represents another piece of the complete physical design solution that we’re bringing to our customers.”
Price and Availability
The Apogee top-level design tool is available now for adding to the Aprisa solution. US pricing starts at $250,000.
ATopTech is demonstrating the Apogee tool, with the Aprisa physical design solution, in its Design Automation Conference booth (#3167) at the Moscone Center in San Francisco, July 27 – 30, 2009. To register for a suite appointment visit www.atoptech.com.
About ATopTech
ATopTech, Inc., is a technology leader in IC physical design. Its Precision Optimization technology offers real design closure at 65 nm and below. The company’s first product family, Aprisa, has extremely close correlation to golden sign-off tools, produces design rule check (DRC)-clean designs, features MCMM optimization at all phases, and offers 10-15 percent better timing and up to 10 percent less standard cell area than existing tools. Use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see http://www.atoptech.com.
Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
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