The Low Power Coalition (LPC) of Si2 has defined and published a power-aware reference flow that is recommended to the industry, including the power closure points and information available throughout the flow, from Electronic System Level (ESL) through implementation. This flow will be discussed. To aid in automating many of the steps along the tool chain, a draft power intent data model and associated Application Procedural Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model, and we will provide an early view of this data model and API.
In addition, enhancements have been made to extend the Common Power Format (CPF), an Si2 standard first released as v1.0 in March 2007 and v1.1 in September, 2008. The current status and future direction of the format will be presented, including progress since the last Low Power Workshop at DAC 2008, goals and plans for interoperability with P1801, and end-user experiences with the technology developed and implemented so far. A panel will discuss “What’s Next,” to discuss areas in which power flows, models, and formats might be extended to support additional power-aware design approaches, such as adaptive methods, asynchronous methods, etc. A selection of advanced tools that have been developed by some of the EDA companies to improve power-aware design will also be presented.
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Program: |
| Introduction to the Low Power Coalition: |
| Gill Watt, AMD – Chairman of the LPC |
| Low Power Design Interoperability Requirements: Looking Ahead! |
| Qi Wang, Cadence, Vice Chair of the LPC Technical Steering Group |
| LPC Modeling Requirements for a Low Power Flow |
| Jerry Frenkil, Sequence, Member, LPC Modeling Working Group |
| LPC Data Model and API |
| Judith Richardson, AMD, Member, Data Model and API WG |
| End-user Adoption Aids |
| Jake Buurma, Si2 |
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EDA Tool Developers for Low Power |
| Steve Carlson, Cadence Design Systems |
| Jerry Frenkil, Sequence Design, Inc. |
| Kiran Vittal, Atrenta, Inc. |
| Anmol Mathur, Calypto Design Systems, Inc. |
| Panel Discussion (all presenters) |
| “What’s next in Low Power” |
Other Si2-sponsored events at DAC include the “Design for Manufacturability Workshop - DFM Challenges at Sub-45nm Design” on July 27, from 1PM-3PM and the Si2 Member/Guest Meeting on July 27, from 6PM-8PM. Both of these events are also free of charge and open to all.
Links to more specific agendas and registration information can be found here: http://www.si2.org/?page=11
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, Entasys, Envis, Global Unichip (TAIEX: 3443), IBM (NYSE: IBM), LSI (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). For further information on the Low Power Coalition, see http://www.si2.org/?page=726.
About Si2
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to-market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world.
Contact:
Silicon Integration Initiative
William Bayer, 512-342-2244, ext.
304 (office)