Averant Announces New Engine, Next Generation Testbench-less Bug Hunting, Support for System Verilog
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Averant Announces New Engine, Next Generation Testbench-less Bug Hunting, Support for System Verilog

HAYWARD, Calif.—(BUSINESS WIRE)—June 5, 2008— Averant Inc., a leading provider of advanced verification technology for RTL designs, today announces the development of significant new technologies, continuing its First In Formal leadership in formal property verification.

Averants engines have been the leaders in the industry for many years now, commented Ramin Hojati, president of Averant. We continue to build on our strength while improving usability and design flow support.

Availability

The new engine is available now. Most of SVD constructs are available now, with the rest becoming available over the summer. Much of next generation bug hunting is available now, but some features will be coming later in the summer.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averants flagship product is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com.



Contact:

Averant, Inc.
Ramin Hojati, +1-510-581-8881 ext. 320
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