For in-depth information about the Design Automation Conference 2008, visit http://www.dac.com/45th/index.aspx.
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| Company: | Altos Design Automation, Inc. | |
| Booth: | 1665 | |
| Media Contact: | Amy Battrell / Jim McCanny | |
| Phone: | 650-363-0142/408-980-8056 | |
| E-mail: | amyb@leepr.com/jmccanny@alto-da.com | |
| Web: | http://www.atlos-da.com | |
| Altos Design Automation (www.altos-da.com) has expanded its characterization technology, going beyond standard cells to support mega-cells and memory. Altos uses proprietary “inside view” techniques to dramatically improve throughput and ease of use. Liberate™ supports advanced timing, noise and power models (CCS, ECSM) and the latest Liberty™ low power constructs. Variety™, part of TSMC’s 8.0 reference flow, generates statistical timing analysis models for multiple tools, including local variation. To learn how to “improve your view” visit Booth #1665 or email info@altos-da.com. | ||
| Company: | AMIQ | |
| Booth: | 682 | |
| Media Contact: | Cristian Amitroaie | |
| Phone: | +40 721 284 254 | |
| E-mail: | cristian@amiq.ro | |
| Web: | www.dvteclipse.com | |
| AMIQ provides ASIC design and verification services. | ||
| Founded 2003, 25 engineers. | ||
| AMIQ brings you DVT, the most complete development environment for E and SystemVerilog, including eRM and OVM support. You get Visual C like capabilities for verification languages. A single unified window combines the editor with the syntax checker, autocomplete, linter, class browser, revision control and other useful tools, which enables fast and smart code development, both for beginners and complex maintenance. For more details visit www.dvteclipse.com. | ||
| Company: | Atrenta, Inc. | |
| Booth: | 2327 | |
| Media Contact: | Amy Battrell / Krishna Uppuluri | |
| Phone: | 650-363-0142/408-453-3333 | |
| E-mail: | amyb@leepr.com/krish@atrenta.com | |
| Web: | http://www.atrenta.com | |
| Atrenta is the leading provider of Early Design Closure(r) solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! | ||
| Company: | Azuro, Inc. | |
| Booth: | 601 | |
| Media Contact: | Michelle Clancy, Cayenne Communications | |
| Phone: | 1 (252) 940-0981 | |
| E-mail: | michelle.clancy@cayennecom.com | |
| Web: | www.azuro.com | |
| Azuro is a provider of EDA tools for clock tree synthesis. The company's unique technology plugs seamlessly into backend design flows, significantly reducing clock tree insertion delay, skew and power without any impact on chip speed or area. Azuro ’ s unique technology delivers significant time-to-market benefits and is being used by leading semiconductor companies around the globe to design cellular modem chips, multimedia chips, network switches, graphics chips, Bluetooth and WiFi chips, embedded processors, PC chipsets, and many other mobile and line powered devices. Founded in 2002, the privately held company is headquartered in Santa Clara, California, with R&D offices in Cambridge, UK. | ||
| Company: | Blue Pearl Software, Inc. | |
| Booth: | 311 | |
| Media Contact: | Ellis Smith | |
| Phone: | 408-961-0121 x 304 | |
| E-mail: | ellis@bluepearlsoftware.com | |
| Web: | www.bluepearlsoftware.com | |
| Blue Pearl Software is a privately held EDA company that develops and markets tools that significantly improve designer productivity and improves the quality of results so chips meet timing and power goals in implementation. | ||
| Cobalt Timing Constraint Generation ™ enables faster timing closure by automatically generating false and multi-cycle path timing exceptions. | ||
| Azure Timing Constraint Validation ™ lowers design risk by automatically validating manually generated false and multi-cycle path timing exceptions. | ||
| Indigo RTL Analysis ™ increases RTL quality by automatically identifying functional design problems such as clock domain crossing synchronization issues, races and simulation/synthesis mismatches. | ||
| Company: |
Breker Verification Systems, Inc. |
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| Booth: | 2741 | |
| Media Contact: | Amy Battrell/Rick Nordin | |
| Phone: | 650-363-0142/512-289-7788 | |
| E-mail: | amyb@leepr.com/rick.nordin@brekersystems.com | |
| Web: | http://brekersystems.com | |
| Breker Verification Systems, Inc. (Austin TX) develops and markets Coverage Model Driven Functional Scenario Generation technology that gives functional verification engineers an automated solution to generating input stimulus, checking output results and measuring scenario coverage. | ||
| Coverage Models combine: 1) graphs and graph constraints to define the space of verification outcomes that must be tested, and 2) the input stimulus required to achieve those outcomes. | ||
| Designed to run in your current verification environment, the Breker technology provides powerful graphical visualization and analysis of a design ’ s verification space. | ||
| Company: | CebaTech Inc. | |
| Booth: | 760 | |
| Media Contact: | Linda Marchant, Cayenne Communications | |
| Phone: | 1 (919) 451-0776 | |
| E-mail: | linda.marchant@cayennecom.com | |
| Web: | www.cebatech.com | |
| CebaTech develops and markets the C2R Compiler ™ , an ESL tool focused on the design entry and verification of advanced ASIC ’ s, FPGA ’ s and SoCs. The compiler automatically generates RTL from standard ANSI C, fits within industry flows and interoperates with traditional Verilog synthesis and simulation tools. Supporting both control and data-path dominated designs, the C2R Compiler dramatically improves engineering productivity and accelerates time to market. CebaTech uses the C2R Compiler to also create a line of licensable IP cores for the network and storage industries. Visit Booth 760 for a demo of the C2R Compiler and to discuss our IP offerings. | ||
| Company: | Fenix Design Automation | |
| Booth: | 534 | |
| Media Contact: | Hein van der Wildt | |
| Phone: | 408-437-7788 | |
| E-mail: | hein@fenix=da.com | |
| Web: | www.fenix-da.com | |
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Fenix-DA has created a much needed set of tools which are applied towards consistency checking of components of the designflow, starting with the enormous variety of library formats. All these different formats (f.i. Verilog, VHDL, .lib, schematic, Spice, lef, Milkyway, just to name a few) present a significant challenge to the chip designer since there are many inconsistencies / inaccuracies amongst these views. |
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| Shrinking geometries and increasing density makes a professional Validation tool a real necessity. Validation checks include both digital and analog libraries and small IP blocks. | ||
| The ultimate goal of Fenix is to offer the client a Quality assessment of the entire designflow, thereby avoiding tape-out delays or re-spins. | ||
| Company: | Gauda, Inc. | |
| Booth: | 323 | |
| Media Contact: | Linda Marchant, Cayenne Communications | |
| Phone: | 1 (919) 451-0776 | |
| E-mail: | linda.marchant@cayennecom.com | |
| Web: | www.gauda.com | |
| At DAC, Gauda will demonstrate how it can accelerate OPC (optical proximity correction) and verification 200 times faster than traditional solutions and that runs on today ’ s desktop computers. Gauda technology, introduced in late February 2008, achieves breakthrough acceleration without any specialized hardware or FPGAs, speeding “ time to mask. ” The company has developed a new breed of algorithms utilizing CPUs and GPUs (graphical processing units) that are traditionally used for gaming. With Gauda technology and approximately 10 all-commodity desktop computers, a large 45nm full-chip layout can be decorated overnight. A single desktop computer is sufficient to complete verification overnight. | ||
| Company: | Hummingbird ® , Open Text Connectivity | |
| Booth: | 774 | |
| Ticker Symbol & Exchange: | NASDAQ: OTEX, TSX: OTC | |
| Media Contact: | Stephanie Dodge | |
| Phone: | 1 519 888 7111 x 2429 | |
| E-mail: | sdodge@opentext.com | |
| Web: | www.hummingbird.com | |
| Hummingbird ® , The Open Text Connectivity Solutions Group is a software company that connects people, data and applications in mission-critical environments through its complete line of remote application access and data integration solutions. With 90% of Global 2000 companies relying on its award-winning solutions for over 20 years, Hummingbird understands the financial and operational challenges that most organizations face, whether it is multiple systems, disparate data sources or geographically dispersed teams. For more information, please visit: www.hummingbird.com. | ||
| Company: | Legend Design Technology, Inc. | |
| Booth: | 1733 | |
| Media Contact: | Jane Wei | |
| Phone: | 408-748-8888 x234 | |
| E-mail: | Janew@LegendDesign.com | |
| Web: | www.LegendDesign.com | |
| Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP library characterization software for SoC designs. With an emphasis on productivity and value, Legend ’ s library characterization toolset, CharFlo-Memory! for memory IP and CharFlo-Cell! for standard cell and IO library, revolutionize the time-consuming and error-prone processes associated with characterization. | ||
| MSIM is Legend ’ s high-accuracy SPICE circuit simulator with fast speed and great convergence. Turbo-MSIM is Legend ’ s full-chip Fast-Spice simulator ideal for timing and power simulation, and mixed-signal circuit verification. Both simulators are well designed for nanometer technology and provide excellent price performance. For more information, visit www.LegendDesign.com. | ||
| Company: | National Instruments | |
| Booth: | 659 | |
| Ticker Symbol & Exchange: | NATI | |
| Media Contact: | Jessica Kaiser | |
| Phone: | (512) 683-6823 | |
| E-mail: | Jessica.Kaiser@ni.com | |
| Web: | www.ni.com | |
| National Instruments supplies essential technologies for designing automated test systems – from test development and management software to high-performance PXI modular instrumentation. The company ’ s virtual instrumentation design software, NI LabVIEW, provides engineers with a highly-productive set of tools for acquiring, analyzing, and presenting test data from today ’ s popular instrumentation platforms. Engineers seeking a new level of flexibility and performance in their test systems combine LabVIEW with PXI modular instrumentation. These compact, high-performance measurement systems feature advanced timing and synchronization technologies and the latest PC technologies, providing high throughput for measurements from 7 ½ -digit DC to 6.6 GHz. For more information, visit ni.com/automatedtest. | ||
| Company: | OCP International Partnership | |
| Booth: | 1840 | |
| Media Contact: | Joe Basques | |
| Phone: | (650) 219-2641 | |
| E-mail: | joe@vitalcompr.com | |
| Web: | www.ocpip.org | |
| OCP International Partnership Association, Inc. (OCP-IP) is an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP). OCP is the first fully supported, openly licensed, comprehensive, interface socket for semiconductor IP cores. | ||
| The mission of OCP-IP is to address problems relating to design, verification, and testing which are common to IP core reuse in "plug and play" System-on-Chip (SoC) products. This initiative comprehensively fulfills system-level integration requirements by promoting IP core reusability and reducing design time, risk and manufacturing costs for SoC designs. | ||
| Company: | OptEM Engineering Inc. | |
| Booth: | 937 | |
| Media Contact: | Joan Beckett | |
| Phone: | 403-289-0499 | |
| E-mail: | jbeckett@optem.com | |
| Web: | http://www.optem.com | |
| OptEM Engineering Inc. is a privately owned computer-aided engineering (CAE) software and consulting services company specializing in the electromagnetic and signal integrity analysis of electronic interconnects. OptEM's software and services focus on interconnect design, extraction, modeling and analysis. Applications include deep-submicron ICs, advanced IC packages, and connector/cable systems, with customers located worldwide. Key software products include OptEM Inspector for submicron interconnect and substrate RC extraction, and OptEM Cable Designer for the design and modeling of high-performance twisted-pair cables. For pricing and licensing information contact OptEM at info@optem.com or call 1-403-289-0499. | ||
| Company: | Paradigm Works, Inc. | |
| Booth: | 2318 | |
| Media Contact: | Saeed Coates | |
| Phone: | 978-289-2808 | |
| E-mail: | saeed.coates@alum.rpi.edu | |
| Web: | www.paradigm-works.com | |
| Paradigm Works is a leading chip design and verification services company recognized for engineering excellence, integrity in business, and overall productivity and cost effectiveness. We provide expert consultants and contractors both on site and offshore, and leverage Paradigm Works' software and productivity accelerators to help clients bring their innovations to market as quickly as possible. | ||
| Paradigm Works' SystemVerilog FrameWorks ™ functional verification tool delivers best-learned practices from thousands of hours of production-proven project experience in an easy to use package that enables rapid chip verification project rampup. FrameWorks is a platform for a complete verification solution and is architected to be simulator independent and supports industry standard functional verification methodologies. | ||
| Paradigm Works will be exhibiting at the 45th DAC (2008) in Booth 2318. | ||
| Company: | Synapse Design Automation | |
| Booth: | 671 | |
| Phone: | 408-206-4648 | |
| E-mail: | satish@synapse-da.com | |
| Web: | www.synapse-da.com | |
| Synapse is a Design Service Company specializing in ASIC/SOC & FPGA | ||
| Expertise in low-power and high-performance designs | ||
| Extensive experience in 45nm and beyond | ||
| Domain knowledge in wireless, networking, storage, flash, graphics, micro-processors | ||
| RTL design/verification, synthesis/STA, DFT, Physical Design/Verification & Bring-up | ||
| Stringently qualified dynamic engineering team | ||
| Cost-effective statistical based methodology for speedy project completion | ||
| Multiple tapeouts with Magma, Synopsys, Cadence & Mentor | ||
| Supplement Fortune 500 companies to achieve challenging milestones | ||
| Company: | Tuscany Design Automation, Inc. | |
| Booth: | 2661 | |
| Media Contact: | Amy Battrell/Tom Kozas | |
| Phone: | 650-363-0142/970-377-0717 | |
| E-mail: |
amyb@leepr.com/tom@tuscanyda.com |
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| Web: | http://www.tuscanyda.com | |
| Tuscany ® develops and markets IC design software that help chip designers achieve wickedly high performance chips – such as microprocessor, graphics, or DSP chips at 90 nm, 65 nm, and below. Tuscany tools provide tremendous physical design capacity, expandability, and extensibility that enable designers to visualize, analyze, and optimize designs using complete design data through its Badger Designer Platform and a rich portfolio of Badger Platform Plug-ins. The Badger Platform and Plug-ins enable design teams to customize or tailor their design methodology to address a variety of issues through out the design flow in order to deliver chips on time, on budget, every time. | ||
| Company: | Z Circuit Automation, Inc. | |
| Booth: | 941 | |
| Media Contact: | Roxanne Reichel | |
| Phone: | 408-201-2240 | |
| E-mail: | roxreichel@z-circuit.com | |
| Web: | www.z-circuit.com | |
| ZChar breaks the one minute barrier. Z Circuit Automation, a leader in cell library characterization and analysis EDA software, has released ZChar-MS, the first characterization system that can generate flip-flop models in less than one minute. This new technology represents a 10x to 20x speed improvement over other systems. Z Circuit will be demonstrating ZChar and it ’ s complete line of library tools for standard cell, memory, and IO pad characterization at the 45th Design Automation Conference. Please visit www.z-circuit.com to sign up for a demo. | ||
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