Cadence President and CEO Mike Fister introduced a new aspect of Cadence solutions for advanced node designs -- designs at 65-nanometers and below. The new core technologies provide a major upgrade to the Cadence® Virtuoso® custom design platform with IC 6.1.3 and Virtuoso Multi-Mode Simulation 7.0 release. The new Spectre turbo technology offered in the Virtuoso Spectre XL product addresses a broad variety of challenges across all analog design methodologies and process nodes by delivering a five to 10 times performance gain over existing solutions without any loss in accuracy. These new capabilities help chip makers accelerate volume production of large, complex designs, especially at advanced node processes of 65 nanometers and below.
Guest speaker Prof. Dr. Mario Theissen, BMW Motorsport Director, spoke about the latest technological developments being used by the BMW Sauber F1 team.
"Our vision for CDNLive! EMEA this year was based around networking and enabling the exchange of ideas in order to meet the challenges of the electronic design industry," said Alexander Duesener, group marketing director, EMEA, Cadence Design Systems. "We wanted to offer European designers a platform to facilitate interactive discussions, and the great feedback given by participants proved this concept to be a success. Early feedback of a survey among participants showed that 73% of attendees stated that the overall technical content of our user conference offered high or very high value, and 94% want to return to future CDNLive! events."
In addition to designers currently working in the industry, attendees included key members of the Cadence European academic network, furthering the company's mission to strengthen links between business and academia. During the event, the winners of the first European University Design Award were announced. Twenty student teams from all over Europe had participated in the contest and the broad spectrum of papers submitted targeted challenges of electronic design, like reduction of power consumption or heat development in complex chips for automotive or consumer applications.
The user conference also included speakers from Cadence and a number of other companies presenting a range of technical papers. Participants were invited to vote for the best user-authored technical paper/presentation in each track. The winners are as follows:
Custom IC design track
James Brodrick, CTO, Toric Ltd
Paper: A novel multiple clock generator - eliminating multiple PLLs
Digital IC design track
Michel Korenhof, IC Designer, NXP
Paper: Experiences from a CPF enabled low power design from RTL-GDS2
Functional verification track
Steve D'Onofrio, Paradigm Works
Paper: Migrating existing AVM- and URM-based testbenches to OVM-based testbench
Silicon-package-board co-design track
Robert Blake, Product Marketing Manager, Altera
Paper: Challenges in implementing DDR3 memory interface on PCB systems - a methodology for interfacing DDR3 SDRAM DIMM to an FPGA
Logic Design track
Bridget Hooser, Senior Design Engineer, Freescale Semiconductor
Paper: Some experiences utilizing IP-XACT/SPIRIT within the verification environment of a real project
About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, Virtuoso and Spectre are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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For more information, please contact: Andrea Huse Sr PR Manager EMEA Cadence Design Systems, GmbH Email Contact