Company leverages ubiquity of C to transform software to silicon and break the IC verification bottleneck
CebaTech makes it possible for IC design teams to take a software-centric approach to hardware design. Using CebaTech's solutions, designers can generate correct embodiments of register transfer level (RTL) hardware derived from working and verified software, effectively eliminating the need for RTL simulation, the IC verification bottleneck. CebaTech was founded in 2004 by a team of technology and business professionals with over 20 years experience working together. The team has experience in IC design, EDA, communication systems, storage design, and manufacturing in large and small corporations, including IBM, Lucent, Nortel, Intel, 3Com, Ansoft, Connectware, and Sandgate Technologies.
CebaTech's wealth of domain expertise developing high-performance ASIC solutions for networking clients has enabled the company to pioneer both Internet Protocol intellectual property cores and an aggressive software-centric ESL chip design methodology. The company's network hardware experts understand the challenges and risks of hardware development. CebaTech's ESL technology enables an entire system on chip (SoC) to be coded in C and run in a native C software environment, where running the tool-generated cycle-accurate C will precisely represent the behavior of the generated RTL running in an HDL simulator. This approach allows extensive verification of the software and consequent hardware design in a pure software environment.
"CebaTech's deep knowledge of IC design and software development allowed them to develop a new design approach as design complexity has increased. The company's approach to turning software into silicon has been used internally to produce a TCP/IP engine that was licensed to a major semiconductor company. Few start-ups have proof-of-concept before they even launch their first EDA product. These were among the compelling reasons why 2M invested in this company," said Steven Leeke, Partner, 2M Companies, Inc.
CebaTech's first intellectual property blocks have been identified as a set of communication protocols derived from open source code. These communication protocols will scale from 1 Gbps to 10 Gbps and will simplify and speed to market a new generation of storage, security and networking products.
"CebaTech technology allows developers to make a radical advance in hardware development and to solve previously intractable problems in functional design verification," said Tim Sullivan, founder and CEO, CebaTech. "By delivering intellectual property blocks that can be dropped into place by hardware developers, we eliminate the need for these developers to create RTL implementations of highly complex protocols-- a tremendous boost to design teams in terms of manpower resources and time required to implement SoCs."
As CebaTech IP blocks are tremendously more complex than the traditional intellectual property blocks used in the FPGA or ASIC industries, the company developed a compiler/ electronic design automation (EDA) toolset that creates synthesizable RTL for integrated circuits (ICs) from C source code.
"Verification has become the major bottleneck in IC development. It takes too much time and costs too much money to verify hardware designs in an RTL simulator. CebaTech's innovative approach--development of designs using untimed C, verification in a native C environment, and then compilation of the C code to cycle accurate C (CAC) for cycle-accurate verification in a live environment -- will enable a huge reduction in verification time and eliminate simulation from the development phase as well as eliminating re-spins due to inadequate verification coverage," said Chad Spackman, CTO, CebaTech, Inc. "Our flow allows engineers to create new chip designs on a dramatically shortened timescale, with significant increases in reliability, higher performance and lower cost of silicon."
From Software to Silicon
Using C as a programming language for high-level, complex IC design, CebaTech intends to drive the adoption of ESL/ top-down design and to revolutionize IC design by:
- Dramatically shortening the time to market for deployment of chip-based products that embed complex protocols.
- Under the direction of hardware architects, allowing compilation of existing, tested, software directly into hardware, eliminating many of the requirements to write specifications and test benches and manually translate code from existing C implementations into hardware-based (RTL) state machines.
- Enabling functional testing in native C software environments, using live networks (as applicable), executing hundreds of millions of instructions per second, compared with the industry-standard RTL simulation approach, where typically a week or more of machine time is used to perform one second of simulated time.
Founded in early 2004 and headquartered in Eatontown, NJ, CebaTech Inc. develops ESL tools and intellectual property modules that accelerate the development and realization of software algorithms and complex communication protocols in silicon. CebaTech's products will include high-value,10G TCP/IP cores for networking, storage, and communication systems and servers as well as ESL technology that transforms SoC/ASIC/ FPGA development into a top-down design process, alleviating existing verification bottlenecks, reducing costs and accelerating time to market.
CebaTech is privately held, with venture funding from 2M, SAS and NJTC. More information about the company may be found at www.cebatech.com.
Media Contact:
Linda Marchant, Cayenne Communication, 919-451-0776,
Email Contact