SAN JOSE, Calif.—(BUSINESS WIRE)—June 8, 2006— SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, was granted 34 claims on June 6, 2006 under United States Patent number 7,058,869 for its invention of debug, diagnosis, and yield improvement of a scan-based integrated circuit where scan chains are surrounded by pattern generators and response compactors when using a DFT (design-for-test) technology, such as Test Compression or Logic BIST (built-in self-test).

The invention includes an output-mask controller and an output-mask network to allow designers to mask off pre-selected scan cells from being compacted in a specific response compactor. It also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Methods are then proposed to automatically synthesize the output-mask controller, output-mask network, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit. The patented DFD (design-for-debug/diagnosis) inventions are used in SynTest products VirtualScan for ATPG pattern compression and TurboBIST-Logic for self-test, resulting in improved yield, productivity and time-to-market (TTM). The patented inventions also aid in improved debug and diagnosis of Scan-based integrated circuits.

About SynTest

SynTest Technologies, Inc., established in 1990, develops intellectual properties (IPs) for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 25 US/PCT patents of which 5 have been issued and 2 allowed. The Company's products improve an electronic design's quality and reduce overall design and test costs. Various applications that use these IPs include logic BIST, memory BIST, boundary-scan synthesis, scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.

SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: info@syntest.com.

SynTest VirtualScan and TurboBIST-Logic are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.

Acronyms:

ATPG: Automatic Test Program Generation

BIST: Built-In Self-Test

DFT: Design-for-Test

DFD: Design-for-Debug/Diagnosis

IP: Intellectual Property

TTM: Time-to-Market

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Contact:

SynTest Technologies, Inc.
Ravi Apte, 408-720-9956 ext. 300