Marvell pioneered PAM4 technology over a decade ago and leads the industry in PAM4 interconnect shipments. Today, most of the optical interconnects used in data center backend and frontend networks are based on PAM4 technology. As compared to PCIe Gen 5, which was based on NRZ modulation, PCIe Gen 6 and 7 require the use of PAM4 modulation. With its recent PCIe Gen 6 retimer announcement and this PCIe Gen 7 demonstration, Marvell extends its industry-leading PAM4-based optical and copper interconnect portfolio beyond Ethernet and InfiniBand into copper and optical PCIe, CXL and proprietary compute fabric links.
The increasing performance of processors and accelerators combined with the growing size of AI clusters is prompting the need for greater bandwidth speed and capacity. PCIe Gen 7 will enable larger volumes of data to be exchanged between processors to reduce the cost, time and energy required for training or inference. PCIe is the industry standard for inside-server-system connections between CPUs, GPUs, AI accelerators, and other server components. AI models are doubling their computation requirements every six months and are now the primary driver of the PCIe roadmap, with PCIe Gen 7 becoming a requirement.
"AI workloads are driving the evolution of server interconnects, and our PCIe Gen 7 technology is engineered to meet the performance and scalability needs of next-generation AI data centers," said Venu Balasubramonian, vice president of product marketing, Connectivity Business Unit at Marvell. "Our leadership in PAM4 SerDes technology in advanced process nodes enables us to deliver superior performance, low latency, and industry-leading performance, power and latency, providing a critical foundation for accelerated infrastructure."
PCIe Gen 7, operating at 128 gigatransfers per second (GT/s) per lane, enables AI and ML workloads to scale across compute fabrics. It delivers the high performance, low latency, and energy efficiency needed to power next-generation AI clusters, high-performance computing (HPC) systems, and cloud data centers.
Marvell PCIe Gen 7 SerDes is designed using 3nm fabrication technology enabling lower power consumption while delivering superior reach and link margins, that are critical for emerging AI super clusters. SerDes and parallel interconnects serve as high-speed pathways for exchanging data between chips. A rack in a hyperscale data center can contain up to tens of thousands of SerDes links.
Extending PAM4 Leadership
Leveraging its PAM4 SerDes technology leadership and its comprehensive data infrastructure IP, Marvell has created a state-of-the-art connectivity platform that enables leading cloud data center operators to optimize their infrastructure for their unique architectures and workloads. In 2023, Marvell introduced the
Marvell® Nova DSP, the industry's first 1.6T PAM4 DSP. Marvell has also introduced integrated PAM4 DSPs (
Marvell® Perseus) and DSPs optimized for efficiency (
Marvell® Spica Gen2-T) to serve the broadening spectrum of cloud data center link types and use cases. PAM4 technology is also the foundation of the
Marvell® Alaska® A DSP chips optimized for active electrical cable (AEC) applications.
Marvell at the 2024 OCP Global Summit
Join Marvell in booth B1 at the 2024 OCP Global Summit, October 15-17, in San Jose, California.
About Marvell
To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.
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