ELK GROVE, Calif., March 04, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Board of Directors has approved the Verilog-AMS 2023 standard for release.

"Accellera is dedicated to delivering standards to the design and verification community that foster increased productivity," emphasized Lu Dai, Chair of Accellera. "The Verilog-AMS 2023 update significantly bolsters analog-specific functionalities while also facilitating compatibility with the UVM-MS standard, further aligning the standards."

In response to feedback from the community, the Verilog-AMS 2023 standard introduces enhancements to analog constructs, along with clarifications for existing constructs.

Updates to the Verilog-AMS 2023 standard include:

• Dynamic tolerance to event control statements
• Jump statements for analog constructs
• Numerous clarifications such as interrupted transitions, context, and named events
• Additional $receiver_count() function for connect modules
• Compiler directives for UVM-MS
  

“As an avid Verilog-AMS power user myself, I had firsthand feedback on areas within the standard that warranted improvement,” stated Peter Grove, Chair of the SystemVerilog-AMS Working Group. “Our working group members evaluated all feedback and worked together to improve the language. This team effort of EDA companies and users alike demonstrates the continued commitment towards advancing the standard.”

Verilog-AMS benefits users by allowing them to describe and simulate analog and mixed-signal designs using a top-level design methodology as well as the traditional bottom-up approaches. The Verilog-AMS standard supports analog and mixed-signal designs at three levels: transistor/gate, transistor/gate-RTL/behavioral, and mixed transistor/gate-RTL/behavioral circuit levels. Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical, and thermal are important.

The updated standard is available to download fee-free. For more information about the Verilog-AMS 2023 Standard, visit the SystemVerilog-AMS Working Group page. For more information on the history of the Verilog-AMS standard, visit the “ About Verilog-AMS” page.

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for-profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit  www.accellera.org. Find out more about  membership. Follow @accellera on Twitter and  LinkedIn or to comment, please use #accellera. Accellera Global Sponsors are Cadence, Siemens EDA, and Synopsys.

Accellera and Accellera Systems Initiative are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

For more information, contact:

Barbara Benjamin
Public Relations for Accellera Systems Initiative
Phone: +1 503 209 2323
Email: barbara@hipcom.com