SANTA CLARA, Calif., Nov. 10, 2022 (GLOBE NEWSWIRE) --
Astera Labs, a pioneer in purpose-built connectivity solutions for intelligent and accelerated systems, today announced its collaboration with AMD to offer 4th Gen AMD EPYC processors to realize the promise of Compute Express Link™ (CXL). Astera Labs is helping to enable OEM and hyperscale customers to deploy CXL at scale and realize the benefits of memory expansion, increased memory utilization and decreased Total Cost of Ownership (TCO).
Astera Labs’ Leo Memory Connectivity Platform is the industry’s first memory controller to support memory expansion, pooling and sharing for CXL 1.1 and 2.0 capable CPUs. The Leo Smart Memory Controllers and Aries Smart CXL Retimers are designed to seamlessly interoperate with AMD EPYC 9004 Series processors to enable plug-and-play connectivity in new composable and heterogeneous architectures powered by CXL technology.
AMD has a long history of x86 firsts, and the innovation continues in the 4th Gen AMD EPYC processors. The AMD EPYC 9004 Series processors introduce support for highly performant DDR5 DIMMs and fast PCIe 5.0 I/O, which enables the demands of today’s AI and ML applications and the increasing use of accelerators, GPUs, FPGAs, and more. Additionally, the processors include support for CXL 1.1+ memory expansion to help meet the demand for ever larger in-memory workload capacity. With the combination of 4th gen AMD EPYC processors and Astera Labs' Leo Smart Memory Controllers, memory pooling can also be supported to reduce memory stranding.
Sanjay Gajendra, chief business officer, Astera Labs, said, “Our Leo Memory Connectivity Platform and Aries Smart Retimer for CXL is purpose-built with a low-latency, high-bandwidth architecture targeting AI/ML workloads and in-memory database applications for cloud-scale deployment. We value our strategic collaboration with AMD as we work together to deliver performant and reliable CXL solutions for our mutual customers today and continue to innovate and meet the needs of future data centers.”
Ram Peddibhotla, corporate vice president, EPYC product management, AMD, said, “4th Gen AMD EPYC processors continue to raise the bar for workload performance in the modern data center. 4th Gen AMD EPYC processors with CXL 1.1+ support and technologies like Astera Labs’ Leo Smart Memory Controllers will transform our customers’ data center operations by reducing memory bandwidth and capacity bottlenecks, driving lower total cost of ownership, and helping enterprises to address their sustainability goals.”
See CXL memory expansion in action at SC’22
Astera Labs and AMD will demonstrate CXL memory expansion at SC’22 in the CXL Consortium Booth #2838, taking place November 13-18 in Dallas, Texas. Attendees will learn how Leo overcomes processor memory bottlenecks and capacity limitations to increase performance and reduce TCO for applications ranging from Artificial Intelligence and Machine Learning to in-memory databases. To meet with Astera Labs’ memory connectivity experts at SC’22, email
info@asteralabs.com.
Resources:
- Video: Demo of CXL in action with Astera Labs’ Leo Memory Connectivity Platform and 4 th Gen AMD EPYC Processors
- Video: Unlock the full potential of CXL with the Leo Memory Connectivity Platform
- Blog:
Unlocking cloud server performance with CXL
About Astera Labs
Astera Labs Inc. is a leader in purpose-built data and memory connectivity solutions to remove performance bottlenecks throughout the data center. With locations worldwide, the company’s silicon, software, and system-level connectivity solutions help realize the vision of Artificial Intelligence and Machine Learning in the Cloud through CXL™, PCIe®, and Ethernet technologies. For more information about Astera Labs including open positions, visit
www.AsteraLabs.com.
AMD, the AMD Arrow logo, EPYC, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
CONTACT: Lori Zielinski
lori.zielinski@asteralabs.com
