Equivalence checking done properly as designs progress will result in significant reduction in unnecessary iterations, as well as reducing the overall time performing timing closure. Additionally, the analysis will reduce the risk of design failure and ensures highest quality timing constraints before tapeout.
Excellicon solution provides the fastest and most comprehensive approach to TEC independent of any timing engine for highest level of confidence in the analysis. Excellicon provides multi-CPU parallel execution option for most efficient execution of the analysis scalable as designs size grows.
About Excellicon
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products CONstraints MANager, CONstraints CERTifier, ConCert-BT (Budgeting Toolbox) and ConCert-ET (Exceptions Toolbox) address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
For further information contact: Rick Eram
