Reading, UK – 7 December 2020. The problem with assembling IP blocks onto a chip is that it can be hard to work out how they will interact with one another and the memory. Whilst the IP blocks will have been pre-verified individually by the vendors, the key questions are how well they work together and, more importantly, how to optimise this. Sondrel has developed new enhanced workflow modelling tools for this purpose that reduce time to market, cut customer costs and optimise architectural design.
“Synopsys
® has a modelling tool called
Platform Architect™ Ultra,” explained Paul Martin, Head of Architecture at Sondrel. “Its ‘Fast Timed’ IP blocks reveal details of how data is moving on the chip between them, and back and forth to the off- and on-chip memory. We have developed enhanced versions of the Workflow Modelling blocks with the co-operation of Synopsys. These enable us to create accurate transaction models so that we can see exactly how the data moves through the chip’s interconnect fabric and reads/writes to memory. The actual data content is immaterial; it’s how it is handled by the memory and interconnect fabric that is critical to being able to identify bottlenecks and adjust the architecture to optimise the performance of the system.”
The benefit of these enhanced models is that the design can be fine-tuned and optimised for timing without having to run many different simulations in RTL, and the enhanced visibility reduces the iterations required to meet the functional coverage requirements when generating functional verification simulations. Now, just the final functional verification simulation has to be run in RTL as a double check. As a result, verification time is significantly reduced from weeks to days, providing reduced costs for customers as well as faster time to market.
Graham Curren, Sondrel’s Founder and CEO, said, “We are the first company to have created these work flow-based, modelling techniques. The enhancements form part of our Performance Verification Environment (PVE) and are exclusively available to our customers as part of our design service.”
Background
Simulation modelling uses TLM2 “Fast Timed” models of the Memory and Interconnect IP and “workflow” models to accurately emulate the core IP. This enables simulations to be run on the performance of the chip which are hundreds of times faster than running in RTL. This performance analysis enables optimization of a design architecture in days that could take weeks or months using RTL simulation.
Simulation allows detailed analysis of performance bottlenecks, for example, two IP blocks could be trying to access the same memory page at the same time causing ‘thrashing’, creating a bottleneck and slowing the chip down significantly. Big chips have many subsystems moving massive amounts of data around, often with significant latency, so eliminating any bottleneck during the architectural design process is vital.
