How to enforce HDL coding standards and gain the overall design review to meet DO-254 objectives

Presenter: Janusz Kitel, DO-254 Program Manager at Aldec
Thursday, July 2, 2020

Abstract:

The RTCA/DO-254 guidance recommends applicants to define and enforce HDL coding standards. The task starts at the planning process including standard definition, a method how it will be enforced, and in case the process will be automated, how the tool or results will be assessed.

Defining the coding standard is not a trivial task since there is no well-defined and official standard mentioned in the RTCA/DO-254 guidance document. The major question is how a detailed review of the HDL code must be done? Is it enough to enforce the minimum number of well-known best coding practices or we should go deeper into the synthesis phase, design constraints and even clock domain crossing analysis? Such a decision must be made with awareness that the coding standard is not the only DO-254 objective related to the design review.

During this webinar we will show the benefits of using ALINT-PRO™ to enforce the coding standard and to streamline the overall design review to meet DO-254 objectives.

Agenda: 

• Coding Standard for DO-254 Projects
• Automatic and Manual Design Reviews
• Enforcing Coding Standard with ALINT-PRO
• Gaining Design Review with Detailed FSM and CDC Analysis
• Tool Assessment and Qualification
• Live Demo

Event Info                                                                  EU Session  3:00 PM – 4:00 PM CEST  Thursday, July 2, 2020 Register for EU Session US Session  11:00 AM – 12:00 PM PT  Thursday, July 2, 2020 Register for US Session Presenter                                                                  Bio: Janusz Kitel is a DO-254 Program Manager at Aldec. He is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. Janusz has 7 years of experience in requirements engineering and over 12 years of experience in product quality assurance. Janusz received his M.S. in Electronics and Telecommunication from Silesian University of Technology and increased his knowledge around software engineering from complementary studies at AGH University of Science and Technology (Poland). His practical engineering experience includes the areas of functional verification, DO-254 compliance and software development and he has held a wide range of engineering positions that include Application Engineer, Software Developer and Project Manager. View On Demand Webinar View Upcoming Webinars Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.