Abstract:

Many chip design houses combine both simulation and prototyping processes to achieve the highest level of verification quality of their products.  Usually, this process applies for the top-level designs. One of the issues of this approach is the inherent difference between simulation and prototyping environments. In case there is a bug found during prototyping, it is quite difficult to replicate it in the simulation environment. However, there is always a need to do so in order to properly fix the code and verify the fix in simulation. 

The combination of simulation and prototyping verification stages could be applied not only for top-level design, but for the block-level and IP core verification as well. Complex mission-critical IPs, forward error correction IP, etc., may require much more test stimulus than what simulation provides. 

In this webinar, we will outline the efficient IP design verification methodology based on the “Common Testbench” approach. The major parts of the Common Testbench could be re-used between simulation and prototyping. While reducing testbench development time, this approach helps to replicate bugs from the prototyping within the simulation environment. The Common Testbench concept will be illustrated using a design example.

Agenda: 

• IP design Verification Issues
• Simulation and Prototyping for IP designs and large blocks
• The “Common Testbench” Concept
• Randomization in the Common Testbench Environment 
• Developing Verification Components for Common Testbench
• Design Example
• Conclusion
• Q&A

Presenter

Bio: Alexander Gnusin is Verification Methodology specialist art Aldec. Currently, he is responsible for ALINT-PRO product improvements. Alexander Gnusin has 23 years of hands-on Design and Verification experience, gained in well-known design houses - Motorola Semiconductors, IBM, Nortel Networks, Ericsson. As Verification Prime for multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation, hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of technology.

Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.