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November 18-21, Denver Colorado
Booth #228, Aldec Inc.
We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs. Manual partitioning of designs with multiple FPGAs, can take days or even weeks, whereas HES-DVM can perform the task in minutes.
The partitioning software can be used with Aldec’s HES Prototyping boards and as well as 3rd party prototyping boards.
See the Aldec demos at SC19, Booth#228
- DNN-based Traffic Detection Using Xilinx Zynq US+ FPGA – In this demo, traffic detection is done using a Convolutional Neural Network (CNN) on a TySOM-3A-ZU19EG development board. Deep Learning Processing Units (DPUs) are implemented in the FPGA for the acceleration of object detection and recognition, which results in 45fps for three input channels.
- Vibe Motion Detection – a reference design based on ViBe™ Background Subtraction algorithm and HES-HPC™ FPGA-based Accelerator running @1920x1080, 30fps. The image processing background subtraction techniques are utilized to transform and detect moving objects in recorded video. HES-HPC platform provides performance enhancement by utilizing extreme parallel processing capabilities of FPGAs to execute computationally intensive image transformations.
- Automatic Partitioning Design for Multi-FPGA Prototyping - Multi-FPGA partitioning has always been a challenge due to the limited number of FPGA I/Os and FPGA-specific clocking trees. Aldec provides a HES-DVM prototyping toolbox that automates design partitioning for multiple FPGAs and integrates an ultra-fast HES Proto-AXI host bridge.