SAN JOSE, Calif., Sept. 10, 2019 (GLOBE NEWSWIRE) --
WHO:
SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, formal models and post-silicon validation platforms, Design IP and rapid customized VIP and Design IP development.
WHAT: Will demonstrate TileLink VIP used to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs at DVCon India. Another demonstration will showcase Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.
WHEN: Wednesday and Thursday, September 25 and 26. Attendees can schedule demonstrations through: demo@smart-dv.com
WHERE: Radisson Blu Bengaluru in Bangalore, India.
About SmartDV
SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP are compatible with all verification languages, platforms and methodologies supporting all simulation, emulation, FPGA prototyping and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit
SmartDV to learn more.
Connect with SmartDV at:
Linkedin:
https://www.linkedin.com/company/smartdv-technologies/about/
Twitter: @SmartDV
For more information, contact:
Nanette Collins
Public Relations for SmartDV
(617) 437-1822
nanette@nvc.com
