WHO: SiFive, the company founded by the inventors of the RISC-V architecture, and leading provider of commercial RISC-V processor IP and custom SoC solutions, and several co-hosts and ecosystem partners, including:

• Co-hosts: Imagination Technologies, Mentor, Qamcom, Syntacore
• Partners: Antmicro, Credo, IAR Systems, Rambus, SecureRF, UltraSoC

WHAT: The SiFive Tech Symposiums on RISC-V will take place in six cities in Europe throughout the month of May. These highly educational events are free to attend, and present many opportunities for engagement with the hardware community. Each event will feature presentations by industry veterans, ecosystem partners and academic luminaries. Attendees will learn about the RISC-V ecosystem and the SaaS-based approach that is enabling fast access to the custom cores, design platforms, and custom SoC solutions for emerging applications.

WHEN/WHERE:

• Cambridge – May 13, 2019 – Agenda/Registration
• Grenoble – May 15, 2019 – Agenda/Registration
• Stockholm – May 17, 2019 – Agenda/Registration
• Moscow – May 20, 2019 – Agenda/Registration
• Munich – May 23, 2019 – Agenda/Registration
• Amsterdam – May 29, 2019 – Agenda/Registration

About SiFive

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.

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