Vladimir Dmitriev-Zdorov, Mentor, a Siemens Business
Maria Agoston, Tektronix
100+ Gb/s Ethernet Forward Error Correction (FEC) Analysis
Cathy Ye Liu, Broadcom Inc.
A Fast & Simple RFI Mitigation Method without Compromising Signal Integrity
Qiaolei Huang, Missouri University of Science and Technology
Ling Zhang, Missouri University of Science and Technology
Yang Zhong, Missouri University of Science and Technology
Jagan Rajagopalan, Amazon Lab126
Deepak Pai, Amazon Lab126
Chen Chen, Amazon Lab126
Amit Gaikwad, Amazon Lab126
Chulsoon Hwang, Missouri University of Science and Technology
Jun Fan, Missouri University of Science and Technology
Using Multiple Huygens Boxes to Detect & Quantify the Coupling Path from Noise Source to Victim
Antonio Ciccomancini Scogna, Futurewei Technologies Inc.
Jiangqi He, Futurewei Technologies Inc.
Cheng Wei Chang, Huawei
Liu Chen Jun, Huawei
DFE Implementation & Optimization Considerations for Test & Measurement
Kalev Sepp, Signal Integrity Consultant for VESA, Sepson Analytics LLC
How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements
Istvan Novak, Samtec
Jim Nadolny, Samtec
Gary Biddle, Samtec
Ethan Koether, Oracle
Demistifying Edge Launch Connectors
Raul Stavoli, Carlisle IT
Davi Correia, Carlisle IT
Emad Soubh, Carlisle IT
Effect of PCB Fabrication Variations on Interconnect Loss, Delay, Impedance & Identified Material Models for 56-Gbps Interconnect Designs
Alex Manukovsky, Intel
Yuriy Shlepnev, Simberian
Thermal & SI/PI Co-Analysis to Quantify PCB Signal Loss Due to Temperature Variation
Hongfei Yan, Intel
Xiaoning Ye, Intel
Yinglei Ren, Intel
Chunfei Ye, Intel
Accelerating 56G PAM4 Link Equalization Optimization Using Machine Learning-based Analysis
Ting Zhu, Hewlett Packard Enterprise
Yongjin Choi, Hewlett Packard Enterprise
Jacky Chang, Hewlett Packard Enterprise
Chris Cheng, Hewlett Packard Enterprise
DesignCon 2019 is also supported by The Institute of Electrical and Electronics Engineers (IEEE), offering its accreditation to conference attendees. Each conference hour is equivalent to one professional development hour (PDH), and 10 PDH’s result in one continuing education unit (CEU) and an official IEEE certificate. IEEE accreditation can be used to meet training requirements, stand out to future employers, and maintain an engineering license.
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About DesignCon
DesignCon is the world's premier conference for chip, board and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board and systems designers in the country. This three-day technical conference and two-day expo combines technical paper sessions, tutorials, industry panels, product demos and exhibits from the industry's leading experts and solutions providers. More information is available at:
www.designcon.com. DesignCon is organized by is organized by UBM, which in June 2018 combined with Informa PLC to become a leading B2B information services group and the largest B2B Events organizer in the world. To learn more and for the latest news and information, visit
www.ubm.com and
www.informa.com.
A photo accompanying this announcement is available at http://www.globenewswire.com/NewsRoom/AttachmentNg/c9e6d890-a9b2-4c94-a628-ea5f9cd309b6
A photo accompanying this announcement is available at http://www.globenewswire.com/NewsRoom/AttachmentNg/c96c5bf7-818d-49b2-a69e-ef0929e60196
Media Contacts: Lauren Lloyd, (310) 266-4792, DesignConPR@ubm.com Audrey Uchimoto, (310) 496-9423, DesignConPR@ubm.com Tam Nguyen, (424) 410-9797, DesignConPR@ubm.com
