RISC-V Foundation Announces Agenda for RISC-V Workshop in Chennai
Thursday, July 19, 2018
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RISC-V Software Development Methodology for RISC-V Devices with
RTOS and Linux or Both
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When: 9 a.m. – 9:30 a.m. IST
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Who: Kevin McDermott, Imperas Software
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Linux Kernel on RISC-V: Where Do We Stand?
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When: 9:30 a.m. – 10 a.m. IST
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Who: Atish Patra and Damien Le Moal, Western Digital
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A Comprehensive Framework for Power-based Side-channel Leakage
Evaluation of Shakti C-Class
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When: 10 a.m. – 10:30 a.m. IST
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Who: Muhammad Arsath and Chester Rebeiro, IIT Madras
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RISECREEK: From RISC-V Spec to 22FFL Silicon
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When: 11:00 a.m. – 11:30 a.m. IST
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Who: Vinod Ganesan and Gopinathan Muthuswamy, IIT
Madras
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Shakti M-Class Libre RISC-V SoC
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When: 11:30 a.m. – 12:00 p.m. IST
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Who: Luke Leighton, Independent Software Libre
Engineer and Advocate
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SLSV : The Shakti LockStep Verification Framework
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When: 12 p.m. – 12:30 p.m. IST
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Who: Paul George, Shiv Nadar University and Lavanya
Jagan, IIT Madras
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A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power,
Performance and Area (PPA)
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When: 14:00 p.m. – 14:30 p.m. IST
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Who: Kunal Ghosh and Anagha Ghosh, VLSI System
Design Corporation
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Integrating Gen-Z in Server-Class RISC-V Processors
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When: 14:30 p.m. – 15:00 p.m. IST
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Who: Mohan Pathasarathy, HPE
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Formal Specification of the RISC-V Instruction Set Architecture
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When: 15:00 p.m. – 15:30 p.m. IST
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Who: Rishiyur Nikhil & Niraj Sharma, Bluespec
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RISC-V Workshop Chennai Conclusion
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When: 15:30 p.m. – 15:45 p.m. IST
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Who : Rick O’Connor, RISC-V Foundation
