May 16 at Stanford University, Palo Alto, CA
P4-NetFPGA Workflow for Networking Researchers
At the 2017 P4 Developer Day, Xilinx will introduce the P4-NetFPGA workflow for networking researchers, developed in collaboration with Stanford University and the University of Cambridge. The new workflow couples the new Xilinx® P416 to FPGA compilation capability with the Xilinx technology-powered open source NetFPGA SUME platform for networking research (netfpga.org). It allows researchers to easily conduct experiments in hardware operating at line rate. At the Developer Day, there will be a half-day hands-on laboratory allowing attendees to gain experience with P4-NetFPGA, including implementing In-band Network Telemetry.
May 17 at Stanford University, Palo Alto, CA
P416-to-FPGA Compilation Demonstration
At the 2017 P4 Workshop, where the new P416 language specification will be discussed, Xilinx will debut its P416 to FPGA compilation flow based on the Xilinx® SDNet™ Development Environment for Networking. SDNet supports FPGA packet processing rates between 1 Gb/sec and 100 Gb/sec. At the workshop, an industry-first demonstration of joint work by Xilinx Labs and Stanford University will show stateful data plane processing for the TCP protocol implemented by compiling a P416 program to a Xilinx FPGA.
About Xilinx
Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, RFSoCs and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, 5G Wireless, Embedded Vision, and Industrial IoT. For more information, visit
www.xilinx.com.
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Xilinx
Amy Attard
(408) 879-6924
amya@xilinx.com
To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/xilinx-debuts-industry-first-p416-to-fpga-compilation-and-introduces-new-p4-netfpga-workflow-for-networking-researchers-at-p4-industry-events-300456363.html
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