The Renesas MCUs have more IP blocks and complex subsystems than existing designs, with thousands of combinations of potential access conflicts found in those designs. The previous Renesas approach involved a manual process for creating use-case test scenarios, which was very time-consuming due to the large number of combinations that needed to be verified. By replacing its legacy process with the Perspec System Verifier, Renesas achieved the benefits of an efficient, algorithm-based system-level verification solution that enabled the automatic generation of complex test scenarios.
After an intensive evaluation using several production designs, Renesas confirmed that the Perspec technology was easy to deploy and that it integrated seamlessly with its existing testbench environment without any additional configurations. It enabled the generation of C code tests directly from Unified Modeling Language (UML) diagrams, which helped reduce human errors. Running on the Cadence Incisive® Enterprise Simulator and the Cadence Palladium® Z1 Enterprise Emulation Platform, it offered a top-down verification process for system specification that improved reusability as the design specifications changed.
"The Perspec System Verifier was the most practical system verification solution for our advanced MCU designs because of its automated test scenario generation capability," said Toshinori Inoshita, senior manager, Elemental Technology Development Div. 1, Renesas System Design Co., Ltd. "Through our evaluation, we found that the Perspec technology easily detected issues caused by complex combinations of power mode settings and transitions. The technology can help us dramatically improve productivity and deliver our designs to IoT application developers much faster. We're also planning to deploy the Perspec technology for our new design projects."
The Perspec System Verifier is a software-driven system-on-chip (SoC) verification solution. It improves SoC quality and saves time by reducing development effort for complex SoC-level use cases, creating coverage-driven automation of system use-case generation, and shrinking the time required to reproduce, debug and fix complex SoC-level bugs. Additionally, it provides a portable stimulus solution by running tests on any logic simulator, emulator, FPGA prototype or silicon.
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SOURCE Cadence Design Systems, Inc.
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