Toshiba Expands Line-up of Industrial Grade e∙MMC™ Ver. 5.1 Compliant Embedded NAND Flash Memory Products

Key Features

  1. The JEDEC e∙MMC Version 5.1 compliant interface handles essential functions, including writing block management, error correction and driver software. It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products. Additionally, new features[4] standardized in JEDEC e∙MMC Version 5.1, such as BKOPS control, Cache Barrier, Cache Flushing Report, Large RPMB Write and Command Queuing, are applied to the new products to enhance usability.
  2. Supports operating temperature range of -40°C to +105°C.
 

Key Specifications

Interface  

JEDEC e∙MMC V5.1 standard
HS-MMC interface

Capacity

8GB, 16GB, 32GB, 64GB

Power Supply Voltage

2.7-3.6V (Memory core)
1.7V-1.95V, 2.7V-3.6V (Interface)

Bus Width x1, x4, x8
Temperature Range -40oC to +105oC
Package  

153Ball FBGA
11.5mm x 13.0mm

 

Notes

[1]  

e•MMC is a product category for a class of embedded memory products built to the JEDEC e•MMC Standard specification and is a trademark of the JEDEC Solid State Technology Association.

[2] Programmable Logic Controller.
[3] Computer on Modules.
[4] BKOPS control” is a function where the host allows the device to perform background operation when the device is idle. “Cache Barrier” is a function that controls when cache data is written to the memory chip. “Cache Flushing Report” is a function that informs the host if the device’s flushing policy is FIFO (First In First Out) or not. “Large RPMB write” is a function that increases the data size that can be written to the RPMB area to 8KB. The “Command Queuing” feature allows users to process multiple tasks generated by the user’s issue of multiple commands, in the order of the user’s preference, by initially storing the tasks in a waiting queue. It improves random read performance speed by approximately 30% at maximum according to Toshiba survey.

Featured Video
Jobs
CAD Engineer for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise